Patents by Inventor Fui Jin Chai

Fui Jin Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7851261
    Abstract: An encapsulated semiconductor package includes a substrate including a chip mounting area and inner contact pads on its upper surface and at least two semiconductor chips, each having an active surface with a plurality of chip contact pads and a passive surface. A first semiconductor chip is mounted on the chip mounting area. A spacer block including a first and a second mounting face lying in essentially parallel planes is positioned between and attached to the first semiconductor chip and a second semiconductor chip. The mounting faces of the spacer block have a rounded outline.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: December 14, 2010
    Assignee: Infineon Technologies AG
    Inventors: Fui Jin Chai, Hai Guan Loh
  • Patent number: 7635642
    Abstract: An integrated circuit includes a first integrated circuit flip chip (105, 205, 305) is bonded to first electric contacts (102, 202, 302) which are an inner part (104, 204, 304) of a planar array (103, 203, 303) of electric contacts. Second electric contacts (106, 206, 306) on the flip chip are in register with the first electric contacts (102, 202, 302) of this inner part of the array. A second integrated circuit (108, 208, 308) is mounted on the face of the flip chip (105, 205, 305) opposite the array. The second integrated circuit (108, 208, 308) has third electric contacts (109, 209, 309) facing away from the flip chip (105, 205, 305). Wire bonds (112, 212, 312) are formed between the third electric contacts of the second integrated circuit (108, 208, 308) and others of the array of first electric contacts (102, 202, 302). The first and second integrated circuits are sealed in a resin body (110, 210, 310).
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: December 22, 2009
    Assignee: Infineon Technologies AG
    Inventor: Fui Jin Chai
  • Publication number: 20060240592
    Abstract: An integrated circuit includes a first integrated circuit flip chip (105, 205, 305) is bonded to first electric contacts (102, 202, 302) which are an inner part (104, 204, 304) of a planar array (103, 203, 303) of electric contacts. Second electric contacts (106, 206, 306) on the flip chip are in register with the first electric contacts (102, 202, 302) of this inner part of the array. A second integrated circuit (108, 208, 308) is mounted on the face of the flip chip (105, 205, 305) opposite the array. The second integrated circuit (108, 208, 308) has third electric contacts (109, 209, 309) facing away from the flip chip (105, 205, 305). Wire bonds (112, 212, 312) are formed between the third electric contacts of the second integrated circuit (108, 208, 308) and others of the array of first electric contacts (102, 202, 302). The first and second integrated circuits are sealed in a resin body (110, 210, 310).
    Type: Application
    Filed: February 27, 2003
    Publication date: October 26, 2006
    Applicant: Infineon Technologies AG
    Inventor: Fui Jin Chai