Abstract: A split gate memory structure including two cells formed on a semiconductor substrate comprises a first conductive line, two dielectric spacers, two conductive spacers, two doping regions, a first dielectric layer and a second conductive line, where the two dielectric spacers, two conductive spacers and two doping regions are symmetrical along the first conductive line. The first conductive line is formed above the semiconductor substrate. The two dielectric spacers are formed beside the two sides of the first conductive line, respectively. The two conductive spacers, e.g., polysilicon spacers, are formed beside the two dielectric spacers, respectively. The two doping regions formed in the semiconductor substrate next to the two conductive spacers, respectively. The first dielectric layer is formed on the two conductive spacers and above the first conductive line. The second conductive line is formed on the first dielectric layer and perpendicular to the two doping regions.

Abstract: A vertical split gate memory cell of silicon-oxide-nitride-oxide-silicon (SONOS) type formed in a trench of a semiconductor substrate includes a first doping region, a second doping region, a conductive line, a conductive plug, a first insulating layer and a second insulating layer, wherein the conductive line and conductive plug serve as a select gate and a control gate of the vertical split gate memory cell, respectively. The first doping region of a first conductive type is underneath the bottom of the trench, whereas the second doping region of the first conductive type is beside the top of the trench. The conductive line serving as the select gate is formed in the bottom of the trench and in operation relation to the first doping region. The first insulating layer is between the conductive line and the first doping region for insulation. The conductive plug is formed above the conductive line, and insulated from the conductive line by the second insulating layer.

Abstract: A vertical split gate memory formed in a trench of a semiconductor substrate comprises a first doping region, a second doping region, a conductive line, a conductive spacer and a conductive plug, wherein the conductive line, conductive spacer and conductive plug serve as a select gate, a floating gate and a control gate of the vertical split gate memory cell, respectively. The first doping region of a first conductive type is underneath the bottom of the trench, whereas the second doping region of the first conductive type is beside the top of the trench. The conductive line serving as the select gate is formed at the bottom of the trench and in operation relation to the first doping region. The conductive spacer is formed beside the sidewall of the trench and above the conductive line. The conductive plug is insulated from the conductive spacer and the conductive line and in operation relation to the conductive spacer.

Abstract: An operation method for non-volatile memory is conducted as follows. First, a non-volatile memory cell capable of storing a first bit and a second bit is provided. The non-volatile memory cell comprises a first region and a second region with a channel therebetween and a gate above the channel but separated therefrom by a charge trapping layer, wherein the first bit and the second bit are positioned close to the first and second regions, respectively. Next, a first programmed voltage for the first bit, a second programmed voltage for the second bit and an erased voltage for the first and second bits are determined, wherein the first programmed voltage is smaller than the second programmed voltage. For reading the first bit, a voltage is applied to the second region, inducing a depletion region around the second region. For reading the second bit, a voltage is applied to the second region, wherein the voltage applied to the second region is smaller than that for reading the first bit.

Abstract: An operation method for non-volatile memory is conducted as follows. First, a non-volatile memory cell capable of storing a first bit and a second bit is provided. The non-volatile memory cell comprises a first region and a second region with a channel therebetween and a gate above the channel but separated therefrom by a charge trapping layer, wherein the first bit and the second bit are positioned close to the first and second regions, respectively. Next, a first programmed voltage for the first bit, a second programmed voltage for the second bit and an erased voltage for the first and second bits are determined, wherein the first programmed voltage is smaller than the second programmed voltage. For reading the first bit, a voltage is applied to the second region, inducing a depletion region around the second region. For reading the second bit, a voltage is applied to the second region, wherein the voltage applied to the second region is smaller than that for reading the first bit.

Abstract: An ONO formation method comprises the following procedures. First, a bottom oxide layer is formed on a silicon substrate, and then a silicon-rich nitride layer is deposited on the bottom oxide layer. Then, an oxidation process is performed to react with silicon atoms in the silicon-rich nitride layer, so as to form a top oxide layer. Alternatively, the silicon-rich layer can be replaced with a combination of a nitride layer and a polysilicon layer. The oxidation process can consume the polysilicon layer into the top oxide layer, and proper oxygen is introduced into the nitride layer.

Abstract: An ONO formation method comprises the following procedures. First, a bottom oxide layer is formed on a silicon substrate, and then a silicon-rich nitride layer is deposited on the bottom oxide layer. Then, an oxidation process is performed to react with silicon atoms in the silicon-rich nitride layer, so as to form a top oxide layer. Alternatively, the silicon-rich layer can be replaced with a combination of a nitride layer and a polysilicon layer. The oxidation process can consume the polysilicon layer into the top oxide layer, and proper oxygen is introduced into the nitride layer.

Abstract: A method of manufacturing a non-volatile memory array having vertical field effect transistors is revealed. First, a semiconductor substrate having multiple trenches is provided, and then dopants are implanted into the semiconductor substrate to form first doping regions and second doping regions respectively serving as source and drain bit lines at different heights. Secondly, a gate dielectric including at least one nitride film, e.g., an oxide/nitride/oxide (ONO) layer, is formed onto the surface of the semiconductor substrate, and polysilicon plugs serving as gate electrodes are filled up the multiple trenches afterward. After that, a polysilicon layer and a tungsten silicide (WiSix) layer are sequentially deposited followed by masking and etching processes to form parallel polycide lines serving as word lines, and then an oxide layer is deposited therebetween and planarized for isolation.