Patents by Inventor Fuji Yang
Fuji Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7808329Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.Type: GrantFiled: August 7, 2008Date of Patent: October 5, 2010Assignee: Agere Systems Inc.Inventors: Kameran Azadet, Fuji Yang
-
Patent number: 7733143Abstract: The present invention implements an apparatus for correcting duty cycle distortion in high speed clock signals. The apparatus includes delay cells that delay each of first and second differential initial clock signals. The apparatus further includes a latch that generates an output clock signal based on the delayed first and second differential initial clock signals. The apparatus further includes a differential feedback buffer that converts the output clock signal into first and second differential feedback signals. The apparatus further includes a feedback circuit that adjusts the delay cells based on the first and second differential feedback signals.Type: GrantFiled: December 21, 2007Date of Patent: June 8, 2010Assignee: Agere Systems Inc.Inventors: Chunbing Guo, Fuji Yang
-
Publication number: 20100034333Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.Type: ApplicationFiled: August 7, 2008Publication date: February 11, 2010Inventors: Kameran Azadet, Fuji Yang
-
Patent number: 7598815Abstract: Multiple carrier frequencies are provided from a phase locked loop, especially closely adjacent quadrature amplitude modulated subcarriers for multiplexed data communications. A quadrature voltage controlled oscillator (VCO) and cascaded frequency dividers provide feedback to a phase comparator to lock the VCO to a reference signal. In addition to frequency divider outputs for use as subcarriers, e.g., binary division factors of the VCO frequency, a quadrature mixer multiplies and adds corresponding quadrature components at two of the frequencies, to generate a differential signal at a difference frequency. The mixer may be outside of the feedback signal path but preferably is in the feedback path to suppress noise. A polyphase filter converts the mixer output to a quadrature signal useful as a subcarrier. The technique efficiently generates sequential integer multiples of a basic frequency, such as sixteen adjacent integer multiples of a frequency reference.Type: GrantFiled: October 3, 2007Date of Patent: October 6, 2009Assignee: Agere Systems Inc.Inventors: Jinghong Chen, Chunbing Guo, Fuji Yang
-
Patent number: 7577225Abstract: Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.Type: GrantFiled: July 28, 2005Date of Patent: August 18, 2009Assignee: Agere Systems Inc.Inventors: Kameran Azadet, Fuji Yang
-
Publication number: 20090160516Abstract: The present invention implements an apparatus for correcting duty cycle distortion in high speed clock signals. The apparatus includes delay cells that delay each of first and second differential initial clock signals. The apparatus further includes a latch that generates an output clock signal based on the delayed first and second differential initial clock signals. The apparatus further includes a differential feedback buffer that converts the output clock signal into first and second differential feedback signals. The apparatus further includes a feedback circuit that adjusts the delay cells based on the first and second differential feedback signals.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Applicant: AGERE SYSTEMS INC.Inventors: Chunbing Guo, Fuji Yang
-
Patent number: 7426247Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer. Each of the plurality of channel-specific receivers is configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator. The interpolator is configured to receive the clock signals from the central frequency synthesizer and couple the phase detector and the central frequency synthesizer.Type: GrantFiled: November 17, 2006Date of Patent: September 16, 2008Assignee: Agere Systems Inc.Inventors: Fuji Yang, Patrick Larsson, Jay O'Neill
-
Publication number: 20080100387Abstract: Multiple carrier frequencies are provided from a phase locked loop, especially closely adjacent quadrature amplitude modulated subcarriers for multiplexed data communications. A quadrature voltage controlled oscillator (VCO) and cascaded frequency dividers provide feedback to a phase comparator to lock the VCO to a reference signal. In addition to frequency divider outputs for use as subcarriers, e.g., binary division factors of the VCO frequency, a quadrature mixer multiplies and adds corresponding quadrature components at two of the frequencies, to generate a differential signal at a difference frequency. The mixer may be outside of the feedback signal path but preferably is in the feedback path to suppress noise. A polyphase filter converts the mixer output to a quadrature signal useful as a subcarrier. The technique efficiently generates sequential integer multiples of a basic frequency, such as sixteen adjacent integer multiples of a frequency reference.Type: ApplicationFiled: October 3, 2007Publication date: May 1, 2008Inventors: Jinghong Chen, Chunbing Guo, Fuji Yang
-
Patent number: 7355451Abstract: A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.Type: GrantFiled: May 31, 2005Date of Patent: April 8, 2008Assignee: Agere Systems Inc.Inventors: Kameran Azadet, Fuji Yang, Chunbing Guo
-
Patent number: 7222290Abstract: A method and apparatus are provided for detecting a receiver over a PCI-Express bus. A receiver is detected on a PCI-Express link by adjusting a common mode voltage using a current injected into one or more transmitter output nodes and detecting whether a receiver is present based on a voltage change rate. The current can be injected, for example, by a charge pump. In various embodiments, the charge pump can be integrated with a CML transmit buffer or an H-bridge type of transmit buffer. The amplitude control circuit can compare the adjusted common mode voltage to one or more predefined voltages and maintain the adjusted common mode voltage between two predefined voltages. The amplitude control circuit provides a signal to the charge pump to control the current injected into the transmitter output nodes. The amplitude control circuit also provides a signal to an exemplary timer that measures the voltage change rate.Type: GrantFiled: April 9, 2004Date of Patent: May 22, 2007Assignee: Agere Systems Inc.Inventors: Chunbing Guo, Fuji Yang
-
Publication number: 20070092039Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer. Each of the plurality of channel-specific receivers is configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator. The interpolator is configured to receive the clock signals from the central frequency synthesizer and couple the phase detector and the central frequency synthesizer.Type: ApplicationFiled: November 17, 2006Publication date: April 26, 2007Applicant: Agere Systems IncorporatedInventors: Fuji Yang, Patrick Larsson, Jay O'Neill
-
Publication number: 20070025490Abstract: Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventors: Kameran Azadet, Fuji Yang
-
Patent number: 7164711Abstract: A digitally programmable analog receive-side channel equalizer includes N identical zero-positioning (ZP) circuit pairs in a cascade, where the transfer function of one ZP circuit of each pair exhibits a positive zero and the transfer function of the other ZP circuit exhibits a negative zero. By digitally controlling tunable capacitors within the pairs, the equalizer's frequency response and gain can be adjusted, while a controllable (e.g., constant) group delay is maintained. The number of blocks in the cascade can be selected, and each block independently configured, to optimally compensate for high-frequency losses in a wide range of transmission environments. One implementation involves a T-block cascade with output taps that feed a T:1 output selector such that the output of the overall equalizer can be selected to be any one of these taps corresponding to a programmable equalizer of effective length N where N?T.Type: GrantFiled: January 22, 2003Date of Patent: January 16, 2007Assignee: Agere Systems Inc.Inventors: Fuji Yang, Fadi Saibi, Chunbing Guo, Kameran Azadet
-
Patent number: 7158587Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes: (1) a PLL-based central frequency synthesizer and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer, each of the plurality including a clock recovery system having a phase detector and a phase interpolator, the clock recovery system coupling the phase detector and the central frequency synthesizer.Type: GrantFiled: September 18, 2001Date of Patent: January 2, 2007Assignee: Agere Systems Inc.Inventors: Fuji Yang, Patrick Larsson, Jay O'Neill
-
Patent number: 7099400Abstract: Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase.Type: GrantFiled: January 22, 2003Date of Patent: August 29, 2006Assignee: Agere Systems Inc.Inventors: Fuji Yang, Michael L. Craner
-
Publication number: 20060017468Abstract: A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.Type: ApplicationFiled: May 31, 2005Publication date: January 26, 2006Applicant: Agere Systems, Inc.Inventors: Kameran Azadet, Fuji Yang, Chunbing Guo
-
Publication number: 20050104623Abstract: A method and apparatus are provided for detecting a receiver over a PCI-Express bus. A receiver is detected on a PCI-Express link by adjusting a common mode voltage using a current injected into one or more transmitter output nodes and detecting whether a receiver is present based on a voltage change rate. The current can be injected, for example, by a charge pump. In various embodiments, the charge pump can be integrated with a CML transmit buffer or an H-bridge type of transmit buffer. The amplitude control circuit can compare the adjusted common mode voltage to one or more predefined voltages and maintain the adjusted common mode voltage between two predefined voltages. The amplitude control circuit provides a signal to the charge pump to control the current injected into the transmitter output nodes. The amplitude control circuit also provides a signal to an exemplary timer that measures the voltage change rate.Type: ApplicationFiled: April 9, 2004Publication date: May 19, 2005Inventors: Chunbing Guo, Fuji Yang
-
Publication number: 20040141567Abstract: Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase.Type: ApplicationFiled: January 22, 2003Publication date: July 22, 2004Inventors: Fuji Yang, Michael L. Craner
-
Publication number: 20040141552Abstract: A digitally programmable analog receive-side channel equalizer includes N identical zero-positioning (ZP) circuit pairs in a cascade, where the transfer function of one ZP circuit of each pair exhibits a positive zero and the transfer function of the other ZP circuit exhibits a negative zero. By digitally controlling tunable capacitors within the pairs, the equalizer's frequency response and gain can be adjusted, while a controllable (e.g., constant) group delay is maintained. The number of blocks in the cascade can be selected, and each block independently configured, to optimally compensate for high-frequency losses in a wide range of transmission environments. One implementation involves a T-block cascade with output taps that feed a T:1 output selector such that the output of the overall equalizer can be selected to be any one of these taps corresponding to a programmable equalizer of effective length N where N≦T.Type: ApplicationFiled: January 22, 2003Publication date: July 22, 2004Inventors: Fuji Yang, Fadi Saibi, Chunbing Guo, Kameran Azadet
-
Patent number: 6586977Abstract: A delay-locked loop (DLL) and a method of performing clock and data recovery. In one embodiment, the DLL includes: (1) a phase detector that generates a phase difference signal based on a phase comparison between a data signal and a mixer output signal of the DLL and (2) a quadrant controller, coupled to the phase detector, that generates first and second voltage control signals based on the phase difference signal and first and second voltage control signals of the DLL.Type: GrantFiled: September 6, 2001Date of Patent: July 1, 2003Assignee: Agere Systems Inc.Inventors: Fuji Yang, Patrick Larsson