Patents by Inventor Fujiaki Nose
Fujiaki Nose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100052149Abstract: A semiconductor device includes: a die pad having a top surface; a plurality of leads arranged around the die pad; a semiconductor chip having a main surface, a back surface, and a plurality of pads formed to the main surface, and having the back surface fixedly adhered in opposing contact with the top surface of the die pad; a plurality of wires electrically connecting the plurality of pads of the semiconductor chip and the plurality of leads, respectively; and a sealing body sealing the semiconductor chip and the plurality of wires. In addition, a plurality of groove portions are formed to a chip-mounting region opposing the back surface of the semiconductor chip in the top surface of the die pad, and an adhesive for fixedly adhering the semiconductor chip to the top surface of the die pad is buried in the plurality of groove portions.Type: ApplicationFiled: August 21, 2009Publication date: March 4, 2010Inventors: Fujiaki Nose, Hiroshi Kikuchi, Norio Nakazato
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Patent number: 7508054Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.Type: GrantFiled: June 16, 2005Date of Patent: March 24, 2009Assignee: Hitachi, Ltd.Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
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Publication number: 20050233501Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.Type: ApplicationFiled: June 16, 2005Publication date: October 20, 2005Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
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Patent number: 6924549Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.Type: GrantFiled: July 18, 2003Date of Patent: August 2, 2005Assignee: Hitachi, Ltd.Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
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Patent number: 6911734Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: GrantFiled: March 20, 2003Date of Patent: June 28, 2005Assignee: Hitachi, Ltd.Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Patent number: 6911733Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: GrantFiled: February 26, 2003Date of Patent: June 28, 2005Assignee: Hitachi, Ltd.Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Patent number: 6876067Abstract: A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating.Type: GrantFiled: March 26, 2003Date of Patent: April 5, 2005Assignee: Hitachi, Ltd.Inventors: Taiga Arai, Fujiaki Nose, Hiroshi Kikuchi, Yoichi Tamaki
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Publication number: 20040041250Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.Type: ApplicationFiled: July 18, 2003Publication date: March 4, 2004Applicant: Hitachi, Ltd.Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
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Publication number: 20030231088Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: ApplicationFiled: February 26, 2003Publication date: December 18, 2003Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Publication number: 20030222281Abstract: A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating.Type: ApplicationFiled: March 26, 2003Publication date: December 4, 2003Applicant: Hitachi, Ltd.Inventors: Taiga Arai, Fujiaki Nose, Hiroshi Kikuchi, Yoichi Tamaki
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Publication number: 20030218238Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: ApplicationFiled: March 20, 2003Publication date: November 27, 2003Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Publication number: 20030042618Abstract: In connection with a semiconductor device which adopts the face down mounting method, it is intended to provide a technique which can check the state of continuity between electrode pads formed on a semiconductor chip and electrode pads formed on a wiring substrate.Type: ApplicationFiled: July 16, 2002Publication date: March 6, 2003Applicant: Hitachi, Ltd.Inventors: Fujiaki Nose, Tomo Shimizu, Hiroshi Kikuchi, Junichi Koike, Masataka Murata