Abstract: The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.

Abstract: The disclosure provides a semiconductor storage device and a reading method that can achieve high-speed processing of error detection and correction and miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip includes a memory array, and a page buffer/sensing circuit including a latch (L1) and a latch (L2). The ECC chip includes RAM_E and RAM_O. The RAM_E and RAM_O hold the read data output from the latches (L1, L2) of the NAND chip. RAM_E holds the data of the even-numbered sectors, and RAM_O holds the data of the odd-numbered sectors. Making RAM_E or RAM_O alternately hold the data of the sectors can reduce the data size of RAM_E and RAM_O.

Abstract: An error detection and correction method for a flash memory includes: a setting step, setting selection information to select a first error detection and correction function for performing 1-bit error detection and correction or a second error detection and correction function for performing multiple-bit error detection and correction; and an executing step, performing the first error detection and correction function or the second error detection and correction function based on the selection information during a read operation or a write operation.

Abstract: The disclosure provides a semiconductor storage device, which can shorten the processing time for error detection and correction. The flash memory of the present disclosure has a NAND chip and an ECC chip. The NAND chip has dedicated input and output terminals which can transmit data with the ECC chip, and the ECC chip has a dedicated input and output terminal which can transmit data with the NAND chip. When reading in the NAND chip, the NAND chip transmits the read data containing the parity data to the ECC chip through the dedicated input and output terminals. The ECC chip detect and correct errors in the read data based on the parity data, and the corrected data is transmitted to the controller through the input and output terminals.

Abstract: The disclosure provides a semiconductor storage device and a reading method that can achieve high-speed processing of error detection and correction and miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip includes a memory array, and a page buffer/sensing circuit including a latch (L1) and a latch (L2). The ECC chip includes RAM_E and RAM_O. The RAM_E and RAM_O hold the read data output from the latches (L1, L2) of the NAND chip. RAM_E holds the data of the even-numbered sectors, and RAM_O holds the data of the odd-numbered sectors. Making RAM_E or RAM_O alternately hold the data of the sectors can reduce the data size of RAM_E and RAM_O.

Abstract: The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2 ; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.

Abstract: An error detection and correction method for a flash memory includes: a setting step, setting selection information to select a first error detection and correction function for performing 1-bit error detection and correction or a second error detection and correction function for performing multiple-bit error detection and correction; and an executing step, performing the first error detection and correction function or the second error detection and correction function based on the selection information during a read operation or a write operation.