Patents by Inventor Fujio Ikegami

Fujio Ikegami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6112208
    Abstract: When input data composed of a symbol string is compressed, bit maps are used. In each bit map, "1" is set to a bit that represents the position of a relevant symbol of the symbol string. In contrast, "0" is set to a bit that represents the position of another symbol of the symbol string. When compressed data is expanded, symbols are expanded in the order thereof. Thus, the positions of symbols that have been expanded are omitted from each bit map. Consequently, each bit map can be shortened and thereby the compression ratio can be improved. Since the length of each bit map is variable, a value of which (the number of symbols expanded by corresponding bit map-2) is added as information for expanding symbols from each variable bit map of the compressed data correctly. In addition, to distinguish data having a bit map from data having no bit map, a flag that represents the presence of a bit map is added to the compressed data.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: August 29, 2000
    Assignee: Fujitsu Limited
    Inventor: Fujio Ikegami
  • Patent number: 4459661
    Abstract: A virtual machine system having a virtual storage function, wherein registers are provided for holding the heading and trailing addresses of the continuous area in the main storage area assigned respectively for each of the plural operating systems. When the main storage area is accessed by a channel or sub-channel, one of the registers is selected, and the heading address of the register selected is added to the main storage address sent from the channel or sub-channel. The added main storage address is compared with the trailing address in the selected register and if the former is smaller than the latter, the overhead for supporting the virtual storage area is reduced by accessing the main storage area in accordance with the added main storage address mentioned above.
    Type: Grant
    Filed: April 21, 1982
    Date of Patent: July 10, 1984
    Assignee: Fujitsu Limited
    Inventors: Saburo Kaneda, Masamichi Ishibashi, Yoshikatsu Seta, Fujio Ikegami
  • Patent number: 4400769
    Abstract: A virtual machine system is provided with a control program for concurrently operating a plurality of OSs (Operating Systems). The object is to suppress the overhead produced when simulating privileged instructions for controlling program status words (PSWs). For this purpose, there is provided simple hardware, in place of the software control conventionally used, including a modification register for storing information required to modify the current PSW information and a pending register for storing pending interrupt information for communication to the corresponding OS.
    Type: Grant
    Filed: October 21, 1980
    Date of Patent: August 23, 1983
    Assignee: Fujitsu Limited
    Inventors: Saburo Kaneda, Naomi Matsumura, Fujio Ikegami, Kazuyuki Shimizu, Yukichi Ikuta
  • Patent number: 4347565
    Abstract: An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.
    Type: Grant
    Filed: November 30, 1979
    Date of Patent: August 31, 1982
    Assignee: Fujitsu Limited
    Inventors: Saburo Kaneda, Takamitsu Tsuchimoto, Kazuyuki Shimizu, Fujio Ikegami