Abstract: At the time of modulating transmission data, TRX 35 error-checks the transmission data and outputs the result of the error check, whereas BB 36 error-checks received data output from TRX 35 and makes a health check based on the result of the error check of the received data and the result of error check output from TRX 35.

Abstract: A base transceiver station includes a baseband signal processor outputting a frequency notification signal indicating a carrier frequency for modulating a baseband signal, in combination with a baseband signal and a radio transmitter and receiver modulating the baseband signal from the baseband signal processor with the carrier frequency designated by the frequency notification signal so as to produce a radio transmission signal. By allowing the baseband signal processor to output the baseband signal and the frequency notification signal to the radio transmitter and receiver, the radio transmitter and receiver is immediately informed of the carrier frequency for modulation of the arriving baseband signal so that the radio transmitter and receiver is capable of generating a radio transmission signal efficiently and properly.

Abstract: A cache memory apparatus and microprocessor therewith has a first address register for a tag memory and a second address register for a data memory, a tag entry decoder and a data entry decoder. Lower order bits of the contents stored in the first address register are transferred to the second address register through a transferring path in a write operation. Tag comparison and a data write of a result of the preceding comparison are executed in parallel in the same clock period, and thereby speed of processing is higher in the case of consecutive write operations at a write hit.

Abstract: An instruction loaded in an instruction register is decoded by an instruction decoder and the branch predicting bit which indicates whether the instruction is branched or not is read out from a branch predicting mechanism. If it is determined that the instruction is a conditional branch instruction as a result of decoding and the instruction is branched as a result of branch prediction, an instruction length and a branch displacement are replaced with each other by a selector, the branch displacement is added to a decoding program counter, and an address of the branch target destination is designated. On the other hand, in an object computer, the branch displacement of the conditional branch instruction is replaced with the instruction length of the conditional branch instruction, the branch condition is inverted, and the changed conditional branch instruction is executed.

Abstract: A device and method for generating execution controlling information (operation designating parameter) for an instruction execution means is provided. The device operates by selecting and composing a parameter (bit field) selected from among the bits of an instruction code and a parameter obtained as a result of decoding the instruction to be executed. The process makes it possible to reduce the size of a micro ROM by processing one instruction having various formats by the same micro-instruction.

Abstract: A device and method for generating execution controlling information (operation designating parameter) for an instruction execution means is provided. The device operates by selecting and composing a parameter (bit field) selected from among the bits of an instruction code and a parameter obtained as a result of decoding the instruction to be executed. The process makes it possible to reduce the size of a micro ROM by processing one instruction having various formats by the same micro-instruction.

Abstract: A pipelined processor to improve the efficiency of conventional pipelined instruction processing including a two stage instruction decoder which converts sets of similar conventional instructions having the general formats: "MOV: A R1 R2" and "MOV: B R1 R2" where the letter fields A,B etc. indicate the direction of data transfer between the registers, R1, R2; into a single format instruction which can be processed by one microprogram. The first stage decoder processes one instruction intact and generates an intermediate code for the remaining format instruction. The second stage decoder utilizes the intermediate code to specify the direction of transfer by reversing the sequence of register numbers in the instruction not processed intact by the first stage. The resulting transfer instructions have the same format and thus require one, rather than two, microprograms for execution, making the pipelined processor more efficient.