Patents by Inventor Fujio Okui

Fujio Okui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12107137
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 ?m from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 1, 2024
    Assignee: FLOSFIA INC.
    Inventors: Mitsuru Okigawa, Fujio Okui, Yasushi Higuchi, Koji Amazutsumi, Hidetaka Shibata, Yuji Kato, Atsushi Terai
  • Publication number: 20240202418
    Abstract: A design support apparatus supports design of a component embedded substrate including an embedded electronic component that configures at least a part of a circuit. The apparatus includes a component information acquiring unit that acquires component information containing component identifying information about the electronic component to be incorporated in the substrate, a pad information acquiring unit that acquires pad information about a type and number of electrode pads to be arranged on the substrate based on the component information, a mounting arrangement information acquiring unit that acquires mounting arrangement information about the arrangement of the substrate and another component on a mounting board in which the component embedded substrate is to be incorporated, and a pad arrangement selecting unit that selects the arrangement of the electrode pad on a surface of the substrate based on the mounting arrangement information and the pad information.
    Type: Application
    Filed: February 2, 2024
    Publication date: June 20, 2024
    Inventors: Masato Ito, Masaya Mitake, Kengo Takeuchi, Toshimi Hitora, Fujio Okui
  • Publication number: 20240176940
    Abstract: Provided is a design support apparatus that supports design of an electronic component embedded substrate, the apparatus including: a height difference calculating unit that calculates a difference between the height of a first electronic component and the height of a second electronic component on the basis of first component information containing height information about the first electronic component to be incorporated in an electronic component embedded substrate and second component information containing height information about the second electronic component to be incorporated in the electronic component embedded substrate; and a height adjustment necessity judging unit that compares the difference with a reference value set in advance, and judges the necessity of a height adjusting member to be arranged on the first electronic component and/or the second electronic component.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Masato Ito, Masaya Mitake, Kengo Takeuchi, Toshimi Hitora, Fujio Okui
  • Publication number: 20230315959
    Abstract: Provided a design support apparatus of supporting design of a component embedded substrate including one or more embedded electronic components that configure at least a part of a circuit, including, a component information acquiring unit that acquires component information about the electronic components to be incorporated in the component embedded substrate; and a required minimum area calculating unit that calculates a required minimum area of a surface of the component embedded substrate on the basis of at least information about a size of each electronic component contained in the component information.
    Type: Application
    Filed: December 28, 2022
    Publication date: October 5, 2023
    Inventors: Masato ITO, Masaya MITAKE, Kengo TAKEUCHI, Toshimi HITORA, Fujio OKUI
  • Publication number: 20220393015
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 ?m from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 8, 2022
    Inventors: Mitsuru OKIGAWA, Fujio OKUI, Yasushi HIGUCHI, Koji AMAZUTSUMI, Hidetaka SHIBATA, Yuji KATO, Atsushi TERAI
  • Publication number: 20220393037
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, a depth d (?m) of the part embedded in the n?-type semiconductor layer satisfying d?1.4; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 8, 2022
    Inventors: Mitsuru OKIGAWA, Fujio OKUI, Yasushi HIGUCHI, Koji AMAZUTSUMI, Hidetaka SHIBATA, Yuji KATO, Atsushi TERAI
  • Patent number: 6008509
    Abstract: A heterostructure insulated-gate field effect transistor comprises a channel layer, barrier layer and a contact layer. The barrier layer is made of a material having an electron affinity smaller than that of the channel layer and equal to that of the contact layer. Due to the single heterostructure, the series resistance between the channel layer and the source (drain) electrode can be decreased without employing complicated selective ion implanting or selective epitaxial growing method.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: December 28, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makoto Inai, Hiroyuki Seto, Fujio Okui, Susumu Fukuda, Hisashi Ariyoshi