Abstract: A signal processing device includes amplifiers that are capable of amplifying detected signals using amplification factors that are different from each other; A/D converters that sample plural signals amplified by the amplifiers using the different amplification factors and output from the amplifiers; calculators that perform, on the basis of the amplification factors of the plural amplifiers, calculation on plural data pieces converted by the A/D converters; and a selector that selects one or more of output data pieces from among plural data pieces output from the calculators.

Abstract: A signal processing device includes amplifiers that are capable of amplifying detected signals using amplification factors that are different from each other; A/D converters that sample plural signals amplified by the amplifiers using the different amplification factors and output from the amplifiers; calculators that perform, on the basis of the amplification factors of the plural amplifiers, calculation on plural data pieces converted by the A/D converters; and a selector that selects one or more of output data pieces from among plural data pieces output from the calculators.

Abstract: For the achievement of data transfer time reduction, removal of noise data, and analytical efficiency improvement in an ADC data processing function of a time-of-flight mass spectrometer, the mass spectrometer comprises a data acquisition circuit including: an ND converter; a signal intensity addition memory that stores data of ion signals such as a time range and the number of measurements and performs an addition process; a voltage value frequency addition memory that performs an addition process of frequencies of voltage values of the predetermined time range and the number of measurements and stores addition results; a threshold level computation circuit that computes a predetermined threshold level from the results in the memory; a compression memory that extracts only data exceeding the threshold level from the data in the signal intensity addition memory; and a counter that controls a measurement time for data acquisition and the operation of each circuit.

Abstract: For the achievement of data transfer time reduction, removal of noise data, and analytical efficiency improvement in an ADC data processing function of a time-of-flight mass spectrometer, the mass spectrometer comprises a data acquisition circuit including: an A/D converter; a signal intensity addition memory that stores data of ion signals such as a time range and the number of measurements and performs an addition process; a voltage value frequency addition memory that performs an addition process of frequencies of voltage values of the predetermined time range and the number of measurements and stores addition results; a threshold level computation circuit that computes a predetermined threshold level from the results in the memory; a compression memory that extracts only data exceeding the threshold level from the data in the signal intensity addition memory; and a counter that controls a measurement time for data acquisition and the operation of each circuit.

Abstract: In a data acquisition system of ADC system, a log amplifier is provided at the pre-stage of an A/D converter, a signal amplified by the log amplifier having a nonlinear input-output characteristic is A/D-converted, and an adding operation of data is performed while reconverting a voltage value data which is converted to a nonlinear characteristic to data with a linear scale according to a table memory for reverse-log conversion. A known voltage value is inputted into the log amplifier to perform measurement, and calibration of the table memory is performed by storing the voltage value and the voltage value data after A/D-converted.

Abstract: The present invention relates to a data processing device for mass spectrometry, in which measurements are performed in a high dynamic range without causing an overrange in an A/D converter in any TOF scan. A data acquisition circuit of a mass spectrometer includes an amplitude value computing circuit which measures and stores a maximum amplitude value of an ion detection signal, a gain control circuit for determining and setting a gain amount for the next measurement, and others. From the immediately preceding TOF scan data or TOF scan data plural times before, the maximum amplitude value of the ion detection signal is extracted. Then, before the next TOF scan, an optimum gain amount is determined based on the extracted maximum amplitude value to adjust the gain of the input signal, and the ion signal is sampled in the A/D converter.

Abstract: In a data acquisition system of ADC system, a log amplifier is provided at the pre-stage of an A/D converter, a signal amplified by the log amplifier having a nonlinear input-output characteristic is A/D-converted, and an adding operation of data is performed while reconverting a voltage value data which is converted to a nonlinear characteristic to data with a linear scale according to a table memory for reverse-log conversion. A known voltage value is inputted into the log amplifier to perform measurement, and calibration of the table memory is performed by storing the voltage value and the voltage value data after A/D-converted.

Abstract: The present invention relates to a data processing device for mass spectrometry, in which measurements are performed in a high dynamic range without causing an overrange in an A/D converter in any TOF scan. A data acquisition circuit of a mass spectrometer includes an amplitude value computing circuit which measures and stores a maximum amplitude value of an ion detection signal, a gain control circuit for determining and setting a gain amount for the next measurement, and others. From the immediately preceding TOF scan data or TOF scan data plural times before, the maximum amplitude value of the ion detection signal is extracted. Then, before the next TOF scan, an optimum gain amount is determined based on the extracted maximum amplitude value to adjust the gain of the input signal, and the ion signal is sampled in the A/D converter.

Abstract: For the achievement of data transfer time reduction, removal of noise data, and analytical efficiency improvement in an ADC data processing function of a time-of-flight mass spectrometer, the mass spectrometer comprises a data acquisition circuit including: an A/D converter; a signal intensity addition memory that stores data of ion signals such as a time range and the number of measurements and performs an addition process; a voltage value frequency addition memory that performs an addition process of frequencies of voltage values of the predetermined time range and the number of measurements and stores addition results; a threshold level computation circuit that computes a predetermined threshold level from the results in the memory; a compression memory that extracts only data exceeding the threshold level from the data in the signal intensity addition memory; and a counter that controls a measurement time for data acquisition and the operation of each circuit.

Abstract: A pulse generation circuit including a pulse formation circuit for generating normal and dummy pulses according to second delay value data, a data calculation circuit for calculating first delay value data at a timing at which the pulses are generated from the pulse formation circuit according to pattern data having information for determining whether to generate pulses from the pulse formation circuit, a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting the no-pulse-generation cycle from the first delay value data, and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: The present invention provides a pulse generation circuit comprising: a pulse formation circuit for generating normal and dummy pulses according to second delay value data; a data calculation circuit for calculating first delay value data being shown a timing at which the pulses is generated from the pulse formation circuit according to pattern data that has information for determining whether to generate pulses from the pulse formation circuit; a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting said no-pulse-generation cycle from said first delay value data; and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit, being disposed between said pulse formation circuit.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.