Patents by Inventor Fujio Shimizu

Fujio Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220005804
    Abstract: A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 6, 2022
    Inventors: Fujio SHIMIZU, Tsuyoshi KACHI, Yoshinori YOSHIDA
  • Patent number: 11152353
    Abstract: A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: October 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Fujio Shimizu, Tsuyoshi Kachi, Yoshinori Yoshida
  • Publication number: 20200402972
    Abstract: A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.
    Type: Application
    Filed: April 17, 2020
    Publication date: December 24, 2020
    Inventors: Fujio SHIMIZU, Tsuyoshi KACHI, Yoshinori YOSHIDA
  • Publication number: 20080078925
    Abstract: An atomic reflection optical element for an atomic wave (de Broglie wave) so constituted as to increase the reflectance of an atomic wave by reducing the apparent atomic density of reflection plane; for example, a porous surface structure, a structure supporting a very thin film, or a structure in which the insular portion (reflection surface) of a reflection-diffraction grating is narrowed is used for this purpose. The above arrangement can provide an atomic reflection optical element having a high atomic wave coherent reflection power.
    Type: Application
    Filed: July 9, 2007
    Publication date: April 3, 2008
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Junichi FUJITA, Fujio Shimizu
  • Patent number: 6689328
    Abstract: In order to improve solid phase diffusion bondability at contact portions between a metal flat foil and a metal corrugated foil together constituting a metal honeycomb body for a catalyst converter used for purifying an exhaust gas and to improve engine durability, the present invention comprises one or combination of the following structures; a structure wherein at least one of the metal foils has a foil thickness of less than 40 &mgr;m; a structure wherein an Al content after bonding is at least 3%; a structure wherein the surface condition of both metal foils in a width-wise direction has a predetermined surface coarseness or a predetermined surface shape and condition; and a structure wherein the width of contact portions between both metal foils is at least five times the thickness of the metal foils.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: February 10, 2004
    Assignee: Nippon Steel Corporation
    Inventors: Tadayuki Otani, Atuhiko Imai, Masayuki Kasuya, Kazutoshi Iwami, Toru Utsumi, Mikio Yamanaka, Hitoshi Ohta, Yoshikuni Tokunaga, Fujio Shimizu, Toshihiro Egami, Tamio Noda
  • Patent number: 6329105
    Abstract: A pattern formation method wherein a very small pattern composed of a desired element (atoms) is formed directly on a substrate by using atomic beam hologram technology. Quantum coherent reflection of an atomic wave is utilized. A coherent atomic beam is irradiated as a material wave, for example, upon a hologram of the transmission type to modulate the atomic beam with pattern information included in the hologram. The atomic beam having passed through and diffracted by the hologram is introduced to a reflecting plane so that the atomic beam may be quantum coherent reflected by the reflecting plane, and the atomic beam thus reflected is introduced into a substrate. A binary (two-value) hologram produced by computer synthesis is used suitably as the hologram. A hologram of the potential control type may be also used.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: December 11, 2001
    Assignee: NEC Corporation
    Inventors: Junichi Fujita, Fujio Shimizu
  • Patent number: 5834769
    Abstract: A hologram is made up from a one-dimensional or two-dimensional slit array, each slit being formed with an electrode pair or electric wire for generating an electric field or magnetic field within the slit. These electric fields or magnetic fields are each set for each slit so as to confer upon an atomic beam passing through the slits a phase shift corresponding to the target hologram reproduced image, thereby allowing the target hologram image to be easily reproduced by directing the atomic beam perpendicular to the hologram surface.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: November 10, 1998
    Assignee: NEC Corporation
    Inventors: Jun-Ichi Fujita, Fujio Shimizu, Shinji Matui
  • Patent number: D348252
    Type: Grant
    Filed: October 5, 1992
    Date of Patent: June 28, 1994
    Assignees: NEC Corporation, Sumitomo Light Metal Industries, Ltd.
    Inventors: Harumi Mizunashi, Yuji Matubara, Sueo Morishige, Yoshio Sato, Fujio Shimizu, Shigetoshi Takasu