Abstract: An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.

Abstract: An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.

Abstract: A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a read current state when a column containing the memory cell is selected.

Abstract: A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected bitline as a sense amplifier input in response to the boosted column enable signal. A sense amplifier produces a data output.

Abstract: A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a read current state when a column containing the memory cell is selected.

Abstract: A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected bitline as a sense amplifier input in response to the boosted column enable signal. A sense amplifier produces a data output.

Abstract: A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier input and a bitline conditioner precharges and readjusts the selected bitline to a precharge threshold. A sense amplifier produces a data output that is based on the sense amplifier input.

Abstract: A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier input and a bitline conditioner precharges and readjusts the selected bitline to a precharge threshold. A sense amplifier produces a data output that is based on the sense amplifier input.

Abstract: An ESD protection circuit for an integrated circuit includes an ESD clamping circuit, an ESD triggering circuit, and an ESD disabling circuit. The ESD clamping circuit is operably coupled to a first power pin of the integrated circuit and a second power pin of the integrated circuit. The ESD triggering circuit is operably coupled to the ESD clamping circuit, wherein, when enabled and when sensing an ESD event, the ESD triggering circuit provides a clamping signal to the ESD clamping circuit such that the ESD clamping circuit provides a low impedance path between the first and second power pins. The ESD disabling circuit is operably coupled to disable the ESD triggering circuit when the integrated circuit is in a normal operating mode.

Abstract: A programmable driver includes a first driver, a second driver, and a controller. The second driver is operably coupled in parallel with the first driver to drive a signal on to a line at a first drive level when a drive control signal is in a first state and wherein, when the drive control signal is in a second state, the second driver is in a high-impedance state such that the first driver drives the signal on to the line at a second drive level, wherein the first drive level is greater than the second drive level. The controller is operably coupled to generate the drive control signal based on load requirements of the line.

Abstract: An ESD protection circuit for an integrated circuit includes an ESD clamping circuit, an ESD triggering circuit, and an ESD disabling circuit. The ESD clamping circuit is operably coupled to a first power pin of the integrated circuit and a second power pin of the integrated circuit. The ESD triggering circuit is operably coupled to the ESD clamping circuit, wherein, when enabled and when sensing an ESD event, the ESD triggering circuit provides a clamping signal to the ESD clamping circuit such that the ESD clamping circuit provides a low impedance path between the first and second power pins. The ESD disabling circuit is operably coupled to disable the ESD triggering circuit when the integrated circuit is in a normal operating mode.

Abstract: An output buffer (100) has a pre-driver circuit (120) for controlling a voltage transition of an output signal from an output driver transistor (150). The pre-driver circuit (120) provides an input that slightly leads the gate voltage of the output driver transistor (150). The pre-driver circuit (120) includes a configurable resistance circuit (480) that provides one resistance value during at the start of a signal transition and provides another resistance value near the end of the signal transition. A threshold detector (470) senses a voltage level of the input signal and switches from one resistance value to the other resistance value when the input signal crosses a predetermined voltage.

Abstract: An output buffer (100) has a pre-driver circuit (120) for controlling a voltage transition of an output signal from an output driver transistor (150). The pre-driver circuit (120) provides an input that slightly leads the gate voltage of the output driver transistor (150). The pre-driver circuit (120) includes a configurable resistance circuit (480) that provides one resistance value at the start of a signal transition and provides another resistance value near the end of the signal transition. A threshold detector (470) senses a voltage level of the input signal and switches from one resistance value to the other resistance value when the input signal crosses a predetermined voltage.

Abstract: An ESD protection circuit (39) coupled to each of a plurality of I/O circuits (30, 32, 36) of an integrated circuit (31) is disclosed. The ESD protection circuit includes a MOSFET transistor (40) to provide primary ESD protection on occurrence of an ESD event. In one embodiment, the control electrode of the MOSFET transistor is coupled to a first buffer circuit (42). Integrated circuit (31) includes a remote trigger circuit (37) coupled to the ESD protection circuits via a trigger bus (47). The individual ESD protection circuits operate in parallel to provide ESD protection to the I/O circuits (30, 32, and 36) upon occurrence of an ESD event.

Abstract: A circuit (600) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (600) includes cascoded NMOSFETs (614, 616), with the upper NMOSFET (614) connected to voltage divider circuitry (628). The voltage divider circuitry (628) provides a first bias voltage to the gate of the upper NMOSFET (614) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately ½ of the drain voltage of the upper NMOSFET (614). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.

Abstract: A method for precharging a selected bitline (20) in a nonvolatile memory array using a boost circuit (54) in parallel to a pull-up device (22) for biasing the bitline. The boost circuit (54) is controlled by a pulse signal (26). One embodiment uses a regulator circuit (56) to isolate the boost circuit (54) from the bitline when the bitline voltage exceeds a threshold voltage level. The regulator triggers a delay circuit (58) which is coupled to a sense amplifier (60). The delay circuit (58) then defers activation of the sense amplifier (60) until the voltage on the selected bitline (20) is below a sense amplifier threshold voltage level.