Abstract: A plastic cover and a vehicle, where the plastic cover includes a main body portion, a surface of the main body portion is provided with a plurality of first protrusions, the plurality of first protrusions are spaced apart and evenly distributed on the surface of the main body portion, each first protrusion is further provided with a plurality of first protruding points, the plurality of first protruding points are spaced apart and evenly distributed on the outer surface of the first protrusion, and the first protrusions, the first protruding points and the main body portion are an integrated molding structure. By providing the protrusions and the protruding points, scratch resistance of the plastic cover can be improved, continuity of scratches can be blocked, and the impact of the scratches on the aesthetics of the plastic cover can be reduced.

Abstract: The present application provides an SFGT storage array, a storage chip, and a data-reading method. The SFGT storage array includes a true semi-floating gate array, a reference semi-floating gate array and a sense amplifier. The true semi-floating gate array includes a plurality of true semi-floating gate storage units, a plurality of first bit lines and a plurality of first word lines. Each of the plurality of first bit lines and each of the plurality of first word lines intersect to operate on one of the true semi-floating gate storage units. Each of the plurality of first bit lines is connected to a first input end of the sense amplifier. The reference semi-floating gate array includes a plurality of second bit lines. Each of the plurality of second bit lines is connected to a second input end of the sense amplifier.

Abstract: The present application provides an SFGT storage array, a storage chip, and a data-reading method. The SFGT storage array includes a true semi-floating gate array, a reference semi-floating gate array and a sense amplifier. The true semi-floating gate array includes a plurality of true semi-floating gate storage units, a plurality of first bit lines and a plurality of first word lines. Each of the plurality of first bit lines and each of the plurality of first word lines intersect to operate on one of the true semi-floating gate storage units. Each of the plurality of first bit lines is connected to a first input end of the sense amplifier. The reference semi-floating gate array includes a plurality of second bit lines. Each of the plurality of second bit lines is connected to a second input end of the sense amplifier.