Patents by Inventor Fukashi Morishita

Fukashi Morishita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230138391
    Abstract: A semiconductor device includes a digital-analog converter provided with a plurality of current cells, and a test circuit electrically connected to the digital-analog converter to test the digital-analog converter. The test circuit includes: a charge information holding circuit that holds, as differential charge information, a difference value between a first charge according to a first current and a second charge according to a second current by at least one or more current cells among the plurality of current cells; a reference voltage generation circuit that generates a reference voltage to be comparative object; and a comparison circuit that compares a determination voltage according to the differential charge information and the reference voltage to output a comparison result.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 4, 2023
    Applicant: Renesas Electronics Corporation
    Inventors: Wataru SAITO, Fukashi MORISHITA
  • Publication number: 20230087101
    Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.
    Type: Application
    Filed: August 11, 2022
    Publication date: March 23, 2023
    Inventors: Yoichi IIZUKA, Fukashi MORISHITA
  • Publication number: 20230022468
    Abstract: An image sensor including an ADC circuit receiving pixel data to be supplied in parallel from the a pixel array, outputting a reference signal in accordance with a digital code, comparing the reference signal and the pixel data, and outputting the digital code at which the reference signal and the pixel data have a predetermined relation, the ADC circuit including a ramp-signal generating circuit outputting a ramp signal having a gradient with respect to change of the digital code, the gradient being different between when the digital code is in a first range and when the digital code is in a second range different from the first range and an attenuator receiving the ramp signal to be supplied and outputting the reference signal having a gradient being the same between when the digital code is in the first range and when the digital code is in the second range.
    Type: Application
    Filed: June 27, 2022
    Publication date: January 26, 2023
    Applicant: Renesas Electronics Corporation.
    Inventor: Fukashi MORISHITA
  • Publication number: 20220408046
    Abstract: A technique capable of improving linearity at a low illuminance is provided. A solid-state sensing image device includes: a pixel array including a plurality pixels arranged in a matrix form and a plurality of pixel signal lines connected to the plurality of pixels and receiving pixel signals supplied from the plurality pixels; a column-parallel A/D converting circuit connected to the plurality of pixel signal lines; and a reference-voltage generating circuit generating ramp-wave reference voltage that linearly changes in accordance with time passage. The column-parallel A/D converting circuit includes a first A/D converter, the first A/D converter includes: a first input terminal connected to the pixel signal line; a second input terminal receiving the reference voltage; and an offset generating circuit connected to the first input terminal and generating an offset voltage for the first input terminal.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 22, 2022
    Inventors: Norihito KATOU, Fukashi MORISHITA
  • Patent number: 11528441
    Abstract: It is an object of the present invention to provide a technique for reducing the variation of a bias voltage. An analog-to-digital converter comprises a comparator including a first amplifier and a second amplifier inputted one output of the first amplifier. The first amplifier is a differential type of amplifier, and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal which changes with a predetermined slope. The second amplifier is a single-ended type amplifier, and determines an auto zero voltage based on the amplified voltage by an auto zero operation of the first amplifier and includes a self-bias circuit using the auto zero voltage as a bias voltage. The comparator is plural, the comparators are plurality which arranged in a row direction, and outputs a digital value based on an analog voltage inputted to the other input terminal in parallel operation.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: December 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Fukashi Morishita
  • Patent number: 11516421
    Abstract: A solid-state imaging device capable of suppressing variations in reference voltages and improving performance of reference voltages is provided. According to one embodiment, the solid-state imaging device includes a pixel outputting a luminance signal voltage corresponding to an amount of incident light, reference voltages, a reference voltage generation circuit outputting a ramp signal and an inverse ramp signal, and an AD converter, and the AD converter includes a comparator including an amplifier coupled to one input terminal, a reference voltage and an input terminal coupled to each of the ramp signals via a capacitor, and an input terminal coupled to each of the reference voltage and the ramp signal via a capacitor, and a ramp current cancel circuit coupled to each of the reference voltages via a cancel capacitor.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 29, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Matsumoto, Masanori Otsuka, Fukashi Morishita
  • Publication number: 20220210364
    Abstract: It is an object of the present invention to provide a technique for reducing the variation of a bias voltage. An analog-to-digital converter comprises a comparator including a first amplifier and a second amplifier inputted one output of the first amplifier. The first amplifier is a differential type of amplifier, and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal which changes with a predetermined slope. The second amplifier is a single-ended type amplifier, and determines an auto zero voltage based on the amplified voltage by an auto zero operation of the first amplifier and includes a self-bias circuit using the auto zero voltage as a bias voltage. The comparator is plural, the comparators are plurality which arranged in a row direction, and outputs a digital value based on an analog voltage inputted to the other input terminal in parallel operation.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 30, 2022
    Inventor: Fukashi MORISHITA
  • Patent number: 11115614
    Abstract: The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC<3:0>, a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC<3:0> and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR<n:3>, and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR<n:3> and an upper bit latch signal 15.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichi Iizuka, Fukashi Morishita
  • Publication number: 20200244908
    Abstract: A solid-state imaging device capable of suppressing variations in reference voltages and improving performance of reference voltages is provided. According to one embodiment, the solid-state imaging device includes a pixel outputting a luminance signal voltage corresponding to an amount of incident light, reference voltages, a reference voltage generation circuit outputting a ramp signal and an inverse ramp signal, and an AD converter, and the AD converter includes a comparator including an amplifier coupled to one input terminal, a reference voltage and an input terminal coupled to each of the ramp signals via a capacitor, and an input terminal coupled to each of the reference voltage and the ramp signal via a capacitor, and a ramp current cancel circuit coupled to each of the reference voltages via a cancel capacitor.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 30, 2020
    Inventors: Osamu MATSUMOTO, Masanori OTSUKA, Fukashi MORISHITA
  • Publication number: 20200195871
    Abstract: The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC<3:0>, a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC<3:0> and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR<n:3>, and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR<n:3> and an upper bit latch signal 15.
    Type: Application
    Filed: October 30, 2019
    Publication date: June 18, 2020
    Inventors: Yoichi IIZUKA, Fukashi MORISHITA
  • Patent number: 10321086
    Abstract: A semiconductor device includes a pixel array including a plurality of pixels arranged in a matrix, each pixel including a first switch and a second switch, a scanning circuit, in a first mode, enabling a first signal to be output from the pixel by setting the first and second switches to “off” in a period before a first timing, enabling a second signal to be output from the pixel by setting only the first switch to “on” for a predetermined period from the first timing, and enabling a third signal to be output from the pixel by setting the first and second switches to “on” for a predetermined period from a second timing after the first timing, and a first AD (Analog/Digital) converter, in a second mode, capable of performing AD conversion by comparing the difference between the second signal and the first signal with a reference signal.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 11, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuhiro Ueda, Fukashi Morishita
  • Patent number: 10257457
    Abstract: Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 9, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Matsumoto, Fukashi Morishita
  • Patent number: 10038868
    Abstract: The present invention provides a technique for achieving higher picture quality of a captured image by reducing noise which occurs at the time of resetting in a solid-state image sensing device and the like. A pixel array in a solid-state image sensing device includes a plurality of pixels and includes an OB pixel region and an effective pixel region. The solid-state image sensing device has a signal processing unit outputting a pixel signal of each of the pixels in the effective pixel region on the basis of the signal level of a signal output from each of the pixels. The solid-state image sensing device obtains a signal without applying a reset signal to each of the pixels in the OB pixel region, obtains the difference between the signal and a signal of a pixel in the effective pixel region, and outputs an image signal.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: July 31, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shunsuke Okura, Fukashi Morishita
  • Publication number: 20180152656
    Abstract: Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 31, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Osamu MATSUMOTO, Fukashi MORISHITA
  • Patent number: 9967502
    Abstract: In a CMOS image sensor, a plurality of bias circuits are dispersedly arranged in an arrangement region of column circuits corresponding to each column of a pixel array. Each bias circuit generates a bias voltage on the basis of a reference current which has been input and supplies the generated bias voltage to the corresponding column circuit 10 which is arranged in the vicinity. Thereby, luminance unevenness of a picked-up image caused by an IR drop of a ground wire for the column circuits is reduced.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: May 8, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Matsumoto, Fukashi Morishita
  • Publication number: 20180007301
    Abstract: A semiconductor device includes a pixel array including a plurality of pixels arranged in a matrix, each pixel including a first switch and a second switch, a scanning circuit, in a first mode, enabling a first signal to be output from the pixel by setting the first and second switches to “off” in a period before a first timing, enabling a second signal to be output from the pixel by setting only the first switch to “on” for a predetermined period from the first timing, and enabling a third signal to be output from the pixel by setting the first and second switches to “on” for a predetermined period from a second timing after the first timing, and a first AD (Analog/Digital) converter, in a second mode, capable of performing AD conversion by comparing the difference between the second signal and the first signal with a reference signal.
    Type: Application
    Filed: September 14, 2017
    Publication date: January 4, 2018
    Inventors: Kazuhiro UEDA, Fukashi MORISHITA
  • Publication number: 20170302875
    Abstract: The present invention makes it possible to read a pixel signal at high speed. A pixel array includes a plurality of pixels that store an electrical charge. The amount of stored electrical charge is based on the amount of received light. A first pixel current source and a second pixel current source are coupled in parallel between a ground voltage and a pixel output node on a pixel signal read line. A switch is disposed in a wiring path that couples the pixel output node, the second pixel current source, and the ground voltage.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Inventors: Shunsuke OKURA, Fukashi MORISHITA
  • Patent number: 9769410
    Abstract: The present invention is directed to solve a problem that, in an imaging element, complicated control is necessary for reading data for focus detection. A scanning circuit makes a first signal output from a pixel by setting first and second switches to “off” in a period before a first timing, makes a second signal output from the pixel by setting only the first switch to “on” for a predetermined period from the first timing, and makes a third signal output from the pixel by setting the first and second switches to “on” for a predetermined period from a second timing after the first timing. A first AD converter performs AD conversion by comparing the difference between the second signal and the first signal with a reference signal. A second AD converter performs AD conversion by comparing the difference between a third signal and the second signal with the reference signal.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: September 19, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhiro Ueda, Fukashi Morishita
  • Patent number: 9716851
    Abstract: The present invention makes it possible to read a pixel signal at high speed. A pixel array includes a plurality of pixels that store an electrical charge. The amount of stored electrical charge is based on the amount of received light. A first pixel current source and a second pixel current source are coupled in parallel between a ground voltage and a pixel output node on a pixel signal read line. A switch is disposed in a wiring path that couples the pixel output node, the second pixel current source, and the ground voltage.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: July 25, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shunsuke Okura, Fukashi Morishita
  • Publication number: 20170118433
    Abstract: The present invention provides a technique for achieving higher picture quality of a captured image by reducing noise which occurs at the time of resetting in a solid-state image sensing device and the like. A pixel array in a solid-state image sensing device includes a plurality of pixels and includes an OB pixel region and an effective pixel region. The solid-state image sensing device has a signal processing unit outputting a pixel signal of each of the pixels in the effective pixel region on the basis of the signal level of a signal output from each of the pixels. The solid-state image sensing device obtains a signal without applying a reset signal to each of the pixels in the OB pixel region, obtains the difference between the signal and a signal of a pixel in the effective pixel region, and outputs an image signal.
    Type: Application
    Filed: January 4, 2017
    Publication date: April 27, 2017
    Inventors: Shunsuke OKURA, Fukashi MORISHITA