Patents by Inventor Fukuji Kihara
Fukuji Kihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7429900Abstract: An object is not only to contribute to reduction in current consumption but also to advance actuation of a system required in a camera, an on-vehicle electric component, etc. by shortening a waiting time for stabilization of oscillation. An oscillator having an inverting amplifier inverting and amplifying an input signal and outputting it, a resonator connected to between an input and an output terminals of the inverting amplifier, a feedback resistance connected in parallel to the resonator, and an output circuit outputting a first clock signal based on a signal of an on-load parallel resonance frequency or a parallel resonance frequency oscillated by the resonator, the inverting amplifier and the feedback resistance to a function block is provided.Type: GrantFiled: September 30, 2005Date of Patent: September 30, 2008Assignees: Fujitsu Limited, Kyocera Kinseki CorporationInventors: Hideo Nunokawa, Fukuji Kihara, Tomonari Morishita, Shunichi Ko, Hiroshi Ookawa
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Patent number: 7196379Abstract: A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.Type: GrantFiled: October 18, 2004Date of Patent: March 27, 2007Assignee: Fujitsu LimitedInventors: Tomonari Morishita, Hideo Nunokawa, Suguru Tachibana, Fukuji Kihara
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Patent number: 7042299Abstract: A crystal oscillation circuit has a reduced circuit area and enables to stably oscillate at low consumed current. The crystal oscillation circuit includes an oscillating amplifier and a constant voltage generator. The oscillating amplifier excites a resonator composed of a resistor, a crystal oscillator and a capacitor. The constant voltage generator includes a one-stage differential circuit composed of a transistor and a capacitor for suppressing transient fluctuation of a constant voltage Vreg for generating the constant voltage Vreg served as a supply voltage for the oscillating amplifier. By generating the constant voltage Vreg through the one-stage differential circuit, the phase lag of the constant voltage Vreg reaches 90 degrees at most. This eliminates the necessity of a phase compensation capacitor, resulting in making the circuit area smaller and realizing the stable oscillation at low consumed current.Type: GrantFiled: April 6, 2005Date of Patent: May 9, 2006Assignee: Fujitsu LimitedInventors: Suguru Tachibana, Tomonari Morishita, Fukuji Kihara, Makoto Kubota
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Publication number: 20060071725Abstract: An object is not only to contribute to reduction in current consumption but also to advance actuation of a system required in a camera, an on-vehicle electric component, etc. by shortening a waiting time for stabilization of oscillation. An oscillator having an inverting amplifier inverting and amplifying an input signal and outputting it, a resonator connected to between an input and an output terminals of the inverting amplifier, a feedback resistance connected in parallel to the resonator, and an output circuit outputting a first clock signal based on a signal of an on-load parallel resonance frequency or a parallel resonance frequency oscillated by the resonator, the inverting amplifier and the feedback resistance to a function block is provided.Type: ApplicationFiled: September 30, 2005Publication date: April 6, 2006Applicants: FUJITSU LIMITED, KYOCERA KINSEKI CORPORATIONInventors: Hideo Nunokawa, Fukuji Kihara, Tomonari Morishita, Shunichi Ko, Hiroshi Ookawa
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Publication number: 20060053399Abstract: A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively wiring unit for tentatively arranging the regulator at the layout position candidates and tentatively laying out a power line, and a regulator layout position deciding unit for deciding a position of a tentative layout at which an area of the power line that is tentatively laid out is the smallest as the layout position of the regulator.Type: ApplicationFiled: December 20, 2004Publication date: March 9, 2006Applicant: Fujitsu LimitedInventors: Hiroyuki Honda, Toshio Arakawa, Hiroshi Mawatari, Norito Hibino, Kouji Arai, Keigo Tada, Fukuji Kihara
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Publication number: 20050280084Abstract: A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.Type: ApplicationFiled: October 18, 2004Publication date: December 22, 2005Inventors: Tomonari Morishita, Hideo Nunokawa, Suguru Tachibana, Fukuji Kihara
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Publication number: 20050174183Abstract: A crystal oscillation circuit has a reduced circuit area and enables to stably oscillate at low consumed current. The crystal oscillation circuit includes an oscillating amplifier and a constant voltage generator. The oscillating amplifier excites a resonator composed of a resistor, a crystal oscillator and a capacitor. The constant voltage generator includes a one-stage differential circuit composed of a transistor and a capacitor for suppressing transient fluctuation of a constant voltage Vreg for generating the constant voltage Vreg served as a supply voltage for the oscillating amplifier. By generating the constant voltage Vreg through the one-stage differential circuit, the phase lag of the constant voltage Vreg reaches 90 degrees at most. This eliminates the necessity of a phase compensation capacitor, resulting in making the circuit area smaller and realizing the stable oscillation at low consumed current.Type: ApplicationFiled: April 6, 2005Publication date: August 11, 2005Inventors: Suguru Tachibana, Tomonari Morishita, Fukuji Kihara, Makoto Kubota
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Patent number: 6781413Abstract: A level conversion circuit for converting a first signal at a lower power source side into a second signal at a higher power source side, which is higher than the lower power source, includes first and second transistors provided at a ground side and controlled by the first signal and an inverted signal there of; third and fourth transistors gates and drains of which are cross-connected, provided at the higher power source side and connected to the first and second transistors respectively; and an initialization circuit for, at a higher power voltage rise time, reducing (or raising), along a current path, a level of either a first node located between the first and third transistors, or a second node located between the second and fourth transistors, to a ground voltage (or to a voltage of the higher power source).Type: GrantFiled: October 16, 2002Date of Patent: August 24, 2004Assignee: Fujitsu LimitedInventors: Fukuji Kihara, Yuki Kaneko
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Publication number: 20030098712Abstract: A level conversion circuit for converting a first signal at a lower power source side into a second signal at a higher power source side, which is higher than the lower power source, comprises: first and second transistors (N4, N6), provided at a ground side and controlled by the first signal and an inverted signal there of; third and fourth transistors (P3, P4) gates and drains of which are cross-connected, provided at the higher power source side and connected to the first and second transistors respectively; and an initialization circuit (20) for, at a higher power voltage rise time, reducing (or raising), along a current path, a level of either a first node located between the first and third transistors, or a second node located between the second and fourth transistors, to a ground voltage (or to a voltage of the higher power source).Type: ApplicationFiled: October 16, 2002Publication date: May 29, 2003Applicant: FUJITSU LIMITEDInventors: Fukuji Kihara, Yuki Kaneko