Abstract: A computer system is provided with a central processing unit (CPU), a bus master coupled to the CPU, and a plurality of interface cards that interface the computer system with peripheral devices. A plurality of host adapters are coupled between the bus master and the interface cards. The host adapters adapt signals between the CPU and the interface cards. Each host adapter generates a ready signal that when asserted indicates readiness of the host adapter to receive address information from the bus master and have data information read by the bus master. An address/data bus is coupled between the bus master and the host adapters. A single separate ready line is coupled between each of the host adapters and the bus master, each ready line carrying the ready signal from a different one of the host adapters to the bus master. The single ready signal carried by a single line serves both an address ready and a data ready signalling function, to thereby, reduce the pin count in the host adapter serving as a slave.