Patents by Inventor Ful Long Ni
Ful Long Ni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Memory structure, programming method and reading method therefor, and memory control circuit thereof
Patent number: 7929365Abstract: A memory structure that improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus, each of the memory units of the memory structure is sensed correctly with its own appropriate set of reference currents, and the improvement of sensing accuracy is therefore achieved.Type: GrantFiled: October 14, 2008Date of Patent: April 19, 2011Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Ful-Long Ni, Chun-Hsiung Hung -
Patent number: 7558149Abstract: One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the appropriate clock signal selects the appropriate measurement type. In another example, multiple clock signals control multiple measurements of a particular location of nonvolatile memory, so that one of multiple clock signals is selected or the appropriate clock signal is generated to apply an appropriate threshold voltage window sensitivity.Type: GrantFiled: December 21, 2006Date of Patent: July 7, 2009Assignee: Macronix International Co., Ltd.Inventors: Chung Kuang Chen, Ful-Long Ni, Yi-Te Shih
-
Memory structure, programming method and reading method therefor, and memory control circuit thereof
Publication number: 20090046521Abstract: The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus each of the memory units of the memory structure of the present invention is sensed with its own appropriate set of reference currents correctly, and the improvement of sensing accuracy is therefore achieved.Type: ApplicationFiled: October 14, 2008Publication date: February 19, 2009Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung-Kuang Chen, Ful-Long Ni, Chun-Hsiung Hung -
Memory structure, programming method and reading method therefor, and memory control circuit thereof
Patent number: 7443753Abstract: The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus each of the memory units of the memory structure of the present invention is sensed with its own appropriate set of reference currents correctly, and the improvement of sensing accuracy is therefore achieved.Type: GrantFiled: November 21, 2006Date of Patent: October 28, 2008Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Ful-Long Ni, Chun-Hsiung Hung -
Memory structure, programming method and reading method therefor, and memory control circuit thereof
Publication number: 20080117703Abstract: The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus each of the memory units of the memory structure of the present invention is sensed with its own appropriate set of reference currents correctly, and the improvement of sensing accuracy is therefore achieved.Type: ApplicationFiled: November 21, 2006Publication date: May 22, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung-Kuang Chen, Ful-Long Ni, Chun-Hsiung Hung -
Patent number: 7330376Abstract: A method for data storage of a memory unit and a memory unit using the same are provided in the present invention. The method for data storage of a memory unit includes: first, dividing a memory unit into a plurality of small memory groups; next, defining a threshold voltage distribution region for each small memory group; then, defining a plurality of program verify threshold voltages and a plurality of reference detecting values for each small memory group according to the threshold voltage distribution region of each small memory group; and after that, using these small memory groups to store data.Type: GrantFiled: July 27, 2006Date of Patent: February 12, 2008Assignee: MACRONIX International Co., Ltd.Inventors: Chung-Kuang Chen, Ful-Long Ni
-
Publication number: 20080025102Abstract: A method for data storage of a memory unit and a memory unit using the same are provided in the present invention. The method for data storage of a memory unit includes: first, dividing a memory unit into a plurality of small memory groups; next, defining a threshold voltage distribution region for each small memory group; then, defining a plurality of program verify threshold voltages and a plurality of reference detecting values for each small memory group according to the threshold voltage distribution region of each small memory group; and after that, using these small memory groups to store data.Type: ApplicationFiled: July 27, 2006Publication date: January 31, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung-Kuang Chen, Ful-Long Ni
-
Publication number: 20070171762Abstract: One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the appropriate clock signal selects the appropriate measurement type. In another example, multiple clock signals control multiple measurements of a particular location of nonvolatile memory, so that one of multiple clock signals is selected or the appropriate clock signal is generated to apply an appropriate threshold voltage window sensitivity.Type: ApplicationFiled: December 21, 2006Publication date: July 26, 2007Applicant: Macronix International Co., Ltd.Inventors: Chung Kuang Chen, Ful-Long Ni, Yi-Te Shih
-
Patent number: 6870752Abstract: The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.Type: GrantFiled: April 23, 2003Date of Patent: March 22, 2005Assignee: Macronix International Co., Ltd.Inventors: Jing-Wen Chen, Ful-Long Ni, Nien-Chao Yang
-
Publication number: 20030235096Abstract: The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.Type: ApplicationFiled: April 23, 2003Publication date: December 25, 2003Inventors: Jing-Wen Chen, Ful-Long Ni, Nien-Chao Yang
-
Patent number: 6621129Abstract: A MROM memory cell structure for storing multi level bit information is disclosed. First of all, a substrate is provided. The substrate has first and second trenches therein, wherein the first trench is deeper than second trench. A conformnal dielectric layer formed on sidewall and bottom of the first and second trenches. A conductive layer filled in the first and second trenches and on the substrate. A first doped region is formed under the first trench. A second doped region is formed under the second trench. A third doped region is formed in surface of the substrate and between the first and second trenches.Type: GrantFiled: May 24, 2002Date of Patent: September 16, 2003Assignee: Macronix International Co., Ltd.Inventors: Chun-Jung Lin, Ful-Long Ni, Chang-Ju Chen
-
Patent number: 6621756Abstract: A compact integrated circuit with memory arrays, shared select transistors and distributed drivers of XDEC is disclosed. The shared select transistors are used to access two adjacent memory cell areas so that the overhead resulting from the conventional select areas can be reduced. The drivers of XDEC are distributed to both sides of the memory arrays to drive the memory cell areas so that conventional transfer areas can be reduced.Type: GrantFiled: November 26, 2001Date of Patent: September 16, 2003Assignee: Macronix International Co., Ltd.Inventors: Chin-Hsi Lin, Meng-Chu Huang, Chun-Li Chen, Ful-Long Ni
-
Publication number: 20030099146Abstract: A compact integrated circuit with memory arrays, shared select transistors and distributed drivers of XDEC is disclosed. The shared select transistors are used to access two adjacent memory cell areas so that the overhead resulting from the conventional select areas can be reduced. The drivers of XDEC are distributed to both sides of the memory arrays to drive the memory cell areas so that conventional transfer areas can be reduced.Type: ApplicationFiled: November 26, 2001Publication date: May 29, 2003Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Hsi Lin, Meng-Chu Huang, Chun-Li Chen, Ful-Long Ni
-
Patent number: 6535432Abstract: A method of erasing a non-volatile memory. The non-volatile memory is positioned on a substrate of a semiconductor wafer and has a memory array region. The memory array region has memory cells, word lines and a substrate line electrically connected to the substrate of each memory cell in the memory array region. The erasing method is to control a potential difference between a word line not to be erased and the substrate to within a specific range, then supply a predetermined first potential to a word line to be erased, thereafter float the word line not to be erased, and finally supply the substrate line with a predetermined second potential. The potential difference between the first and the second potential drive the charges stored in the floating gate of the memory cell electrically connected to the word line to be erased to move into the channel through the tunneling oxide layer to complete the erasing.Type: GrantFiled: June 4, 2001Date of Patent: March 18, 2003Assignee: Macronix International Co. Ltd.Inventors: Ching-Fang Yen, Ful-Long Ni
-
Publication number: 20030051106Abstract: A multi-memory architecture and a memory access controller therefor are proposed. The multi-memory architecture is composed of at least two different types of memory devices and is used to provide a specific externally-accessible data storage capacity. The multi-memory architecture comprises a first memory device and a second memory device; wherein the first memory device has a first data storage capacity; and the second memory device has a second data storage capacity. The pin configuration of the multi-memory architecture is compatible with the first memory device with the externally accessible data storage capacity, wherein the externally-accessible data storage capacity can be either the first data storage capacity, the second data storage capacity, or the sum of the first and second data storage capacties.Type: ApplicationFiled: August 29, 2002Publication date: March 13, 2003Inventors: Ching-Fang Yen, Sheau-Yung Shyu, Ful-Long Ni
-
Patent number: 6525361Abstract: An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.Type: GrantFiled: November 19, 1999Date of Patent: February 25, 2003Assignee: Macronix International Co., Ltd.Inventors: Tao Cheng Lu, Chung Ju Chen, Hon Sui Lin, Mam Tsung Wang, Chin Hsi Lin, Ful Long Ni
-
Publication number: 20020168822Abstract: A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.Type: ApplicationFiled: August 14, 2001Publication date: November 14, 2002Inventors: Chun-Yi Yang, Chun-Jung Lin, Ful-Long Ni
-
Patent number: 6468869Abstract: A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.Type: GrantFiled: August 14, 2001Date of Patent: October 22, 2002Assignee: Macronix International Co., Ltd.Inventors: Chun-Yi Yang, Chun-Jung Lin, Ful-Long Ni
-
Publication number: 20020034854Abstract: An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.Type: ApplicationFiled: July 6, 2001Publication date: March 21, 2002Inventors: Tao Cheng Lu, Chung Ju Chen, Hon Sui Lin, Mam Tsung Wang, Chin Hsi Lin, Ful Long Ni
-
Publication number: 20010050865Abstract: A method of erasing a non-volatile memory. The non-volatile memory is positioned on a substrate of a semiconductor wafer and has a memory array region. The memory array region has memory cells, word lines and a substrate line electrically connected to the substrate of each memory cell in the memory array region. The erasing method is to control a potential difference between a word line not to be erased and the substrate to within a specific range, then supply a predetermined first potential to a word line to be erased, thereafter float the word line not to be erased, and finally supply the substrate line with a predetermined second potential. The potential difference between the first and the second potential drive the charges stored in the floating gate of the memory cell electrically connected to the word line to be erased to move into the channel through the tunneling oxide layer to complete the erasing.Type: ApplicationFiled: June 4, 2001Publication date: December 13, 2001Inventors: Ching-Fang Yen, Ful-Long Ni