Patents by Inventor Fulvio Vittorio Fontana

Fulvio Vittorio Fontana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152289
    Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 19, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi, Michele Derai
  • Publication number: 20210249337
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Cristina SOMMA, Fulvio Vittorio FONTANA
  • Publication number: 20210233884
    Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.
    Type: Application
    Filed: January 26, 2021
    Publication date: July 29, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventor: Fulvio Vittorio FONTANA
  • Patent number: 11004775
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: May 11, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristina Somma, Fulvio Vittorio Fontana
  • Publication number: 20210035894
    Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 4, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventor: Fulvio Vittorio FONTANA
  • Publication number: 20200176363
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Cristina SOMMA, Fulvio Vittorio FONTANA
  • Patent number: 10639661
    Abstract: A device for dispensing a fluid includes a fixed part to be worn by a user, a fluid connection including a terminal outlet, a needle coupled to the terminal outlet of the fluid connection for dispensing a fluid, and a replaceable part coupled to the fixed part via the fluid connection. The replaceable part includes a reservoir for containing the fluid to be dispensed, and a micro-pump coupled to the reservoir to send the fluid to the fixed part through the fluid connection. An actuator operates the micro-pump. The fixed part includes a pressure-sensor in proximity to the terminal outlet of the fluid connection and is associated with dispensing the fluid from the needle. An electronic control module controls operation of the micro-pump via the pressure-sensor.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: May 5, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Fulvio Vittorio Fontana
  • Patent number: 10643940
    Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: May 5, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi
  • Patent number: 10593612
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: March 17, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cristina Somma, Fulvio Vittorio Fontana
  • Patent number: 10593614
    Abstract: In an embodiment, a semiconductor device includes: a lead-frame including one or more electrically conductive areas, one or more dielectric layers over the electrically conductive area or areas, one or more electrically conductive layer over the one or more dielectric layers thus forming one or more capacitors each including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer. The semiconductor device also includes a semiconductor die on the lead-frame electrically connected to the one or more electrically conductive layers.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 17, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi
  • Publication number: 20190348350
    Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 14, 2019
    Inventors: Fulvio Vittorio FONTANA, Giovanni GRAZIOSI, Michele DERAI
  • Publication number: 20190287880
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Application
    Filed: March 19, 2018
    Publication date: September 19, 2019
    Inventors: Cristina SOMMA, Fulvio Vittorio FONTANA
  • Publication number: 20190259691
    Abstract: In an embodiment, a semiconductor device includes: a lead-frame including one or more electrically conductive areas, one or more dielectric layers over the electrically conductive area or areas, one or more electrically conductive layer over the one or more dielectric layers thus forming one or more capacitors each including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer. The semiconductor device also includes a semiconductor die on the lead-frame electrically connected to the one or more electrically conductive layers.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 22, 2019
    Inventors: Fulvio Vittorio FONTANA, Giovanni GRAZIOSI
  • Publication number: 20190148282
    Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 16, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventors: Fulvio Vittorio FONTANA, Giovanni GRAZIOSI
  • Patent number: 10283441
    Abstract: In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 7, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi
  • Patent number: 10211140
    Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi
  • Patent number: 10211129
    Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics S.R.L.
    Inventor: Fulvio Vittorio Fontana
  • Patent number: 10128057
    Abstract: A supercapacitor including: a shell; a chamber in the shell; a first electrode and a second electrode on respective walls of the chamber; and a separator arranged between the first electrode and the second electrode through the chamber. The separator includes a first perforated membrane and a second perforated membrane, which is movable with respect to the first membrane between a first position, in which the first membrane and the second membrane are separate and a second position, in which the first membrane and the second membrane are in contact and coupled for rendering the separator impermeable.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: November 13, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giovanni Scurati, Marco Morelli, Fulvio Vittorio Fontana
  • Patent number: 10026679
    Abstract: A process for manufacturing a surface-mount electronic device includes forming a plurality of preliminary contact regions of a sinterable material on a supporting structure, the supporting structure being of a soluble type. A chip including a semiconductor body is mechanically coupled to the supporting structure. The sinterable material is sintered such that each preliminary contact region forms a corresponding sintered preliminary contact, and the chip and the plurality of preliminary contact regions are coated with a dielectric coating region, and the supporting structure is removed using a jet of liquid.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 17, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Fulvio Vittorio Fontana
  • Patent number: 9972562
    Abstract: A semiconductor device includes: a semiconductor die having first and second opposite surfaces, a die pad having the first surface of the semiconductor die attached thereon, an electrically conductive ground pad at the second surface of the semiconductor die, a device package coupled with the semiconductor die with the ground pad lying between the semiconductor die and the package, and ground wiring or tracks for the semiconductor die between the second surface of the semiconductor die and the ground pad. A further ground connection may be provided between the ground pad at the second surface of the semiconductor die and the die pad having the semiconductor die attached thereon.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: May 15, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Fulvio Vittorio Fontana