Abstract: A method for analyzing a delay time distribution of an N-stage circuit. The method includes a delay time calculation step of calculating maximum deviation delay time of a signal propagating through the circuit and basic delay time of the circuit, a delay variation calculation step of calculating a delay variation value of the N-stage circuit by using the mean square of differences between the maximum deviation delay time of the circuit and the basic delay time of the circuit taken over the N stages, and a step of generating the delay time distribution of the N-stage circuit as a normal distribution by using the calculated delay variation value.

Abstract: A semiconductor memory device having a first memory block used when it is determined to be used in a first case, a second memory block used as an alternative of the first memory blocks when it is determined to be used in a second case, a write section that writes determination data into the first memory block for making a determination at the time of the determination and writes the determination data into the second memory block and a read section that reads the determination data written into the first memory block by the write section for making a determination at the time of the determination and reads the determination data written into the second memory block by the write section.

Abstract: A method for analyzing a delay time distribution of an N-stage circuit. The method includes a delay time calculation step of calculating maximum deviation delay time of a signal propagating through the circuit and basic delay time of the circuit, a delay variation calculation step of calculating a delay variation value of the N-stage circuit by using the mean square of differences between the maximum deviation delay time of the circuit and the basic delay time of the circuit taken over the N stages, and a step of generating the delay time distribution of the N-stage circuit as a normal distribution by using the calculated delay variation value.

Abstract: A semiconductor memory device having a first memory block used when it is determined to be used in a first case, a second memory block used as an alternative of the first memory blocks when it is determined to be used in a second case, a write section that writes determination data into the first memory block for making a determination at the time of the determination and writes the determination data into the second memory block and a read section that reads the determination data written into the first memory block by the write section for making a determination at the time of the determination and reads the determination data written into the second memory block by the write section.

Abstract: A memory device that amplifiers read data based on the timing of a CLK signal input from an external device comprises: a delay circuit 5 that controls a code of the CLK signal and a delay amount based on a CT signal input from an external device to output a CLK_delay signal; a sense enable signal generation section 6 that generates a sense enable signal based on the CLK_delay signal; a memory cell 4 that outputs data in accordance with an instruction from outside; and a sense amplifier 7 that amplifiers the output of the memory cell in accordance with the sense enable signal.

Abstract: A memory device that amplifiers read data based on the timing of a CLK signal input from an external device comprises: a delay circuit 5 that controls a code of the CLK signal and a delay amount based on a CT signal input from an external device to output a CLK_delay signal; a sense enable signal generation section 6 that generates a sense enable signal based on the CLK_delay signal; a memory cell 4 that outputs data in accordance with an instruction from outside; and a sense amplifier 7 that amplifiers the output of the memory cell in accordance with the sense enable signal.