Patents by Inventor Fumiaki Hosaka
Fumiaki Hosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10514740Abstract: A computer device includes a power supply unit which includes an instantaneous power failure resistance capacitor and converts an alternating current into a direct current and outputs the direct current, and a main body which includes a main storage unit having a non-volatile storage area and a processor for executing programs, wherein the power supply unit includes a power failure detection unit which detects that a supply of the alternating current has been stopped, and wherein the main body includes a logical device which, when the detection is notified from the power failure detection unit, instructs the processor within a retention time of the instantaneous power failure resistance capacitor to perform transaction processing of converting data of a buffer in the processor into reusable data and transferring the reusable data to the main storage unit.Type: GrantFiled: January 22, 2016Date of Patent: December 24, 2019Assignee: Hitachi, Ltd.Inventor: Fumiaki Hosaka
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Publication number: 20180267588Abstract: A computer device includes a power supply unit which includes an instantaneous power failure resistance capacitor and converts an alternating current into a direct current and outputs the direct current, and a main body which includes a main storage unit having a non-volatile storage area and a processor for executing programs, wherein the power supply unit includes a power failure detection unit which detects that a supply of the alternating current has been stopped, and wherein the main body includes a logical device which, when the detection is notified from the power failure detection unit, instructs the processor within a retention time of the instantaneous power failure resistance capacitor to perform transaction processing of converting data of a buffer in the processor into reusable data and transferring the reusable data to the main storage unit.Type: ApplicationFiled: January 22, 2016Publication date: September 20, 2018Inventor: Fumiaki HOSAKA
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Patent number: 9836359Abstract: There is provided a storage having plural clusters. Each of the clusters includes a cache memory and a save memory. The processor of each of the clusters controls to write plural data pieces into the cache memory, controls to store all the data stored in the cache memory into the save memory upon an occurrence of a failure, and controls to restore some of the data stored in the save memory into the cache memory upon recovery from the failure.Type: GrantFiled: July 11, 2014Date of Patent: December 5, 2017Assignee: HITACHI, LTD.Inventor: Fumiaki Hosaka
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Publication number: 20160259695Abstract: There is provided a storage having plural clusters. Each of the clusters includes a cache memory and a save memory. The processor of each of the clusters controls to write plural data pieces into the cache memory, controls to store all the data stored in the cache memory into the save memory upon an occurrence of a failure, and controls to restore some of the data stored in the save memory into the cache memory upon recovery from the failure.Type: ApplicationFiled: July 11, 2014Publication date: September 8, 2016Applicant: HITACHI, LTD.Inventor: Fumiaki HOSAKA
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Publication number: 20140189202Abstract: The access performance of a drive having a non-volatile memory is improved. A storage apparatus is provided with a controller, a memory and a drive. When the drive information is decided to satisfy the first condition and the controller receives from the host computer a write request instructing the controller to update first data stored in the drive to second data, the controller transmits to the drive control device a first read command instructing the drive control device to read the first data from the non-volatile memory in accordance with the write request. After the transmission of the first read command, the controller transmits to the drive control device a first write command instructing the drive control device to write the second data to the drive in accordance with the write request.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Applicant: Hitachi, Ltd.Inventor: Fumiaki Hosaka
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Patent number: 8650419Abstract: The charge capacity of a battery for supplying electric power to a volatile memory and a nonvolatile memory is increased without increasing the power source capacity. A control unit for controlling data input/output processing on a storage device is configured by combining a plurality of units which become load on a power source; and at the time of power interruption of a power source, the control unit saves data and information, which are stored in a volatile memory, to a nonvolatile memory. A battery charged by the power source supplies electric power to the volatile memory and the nonvolatile memory at the time of the power interruption. When the electric power is supplied from the power source to the control unit at the time of power recovery after the power interruption, a main controller selects an activation target unit, which is to be activated, from among the plurality of units belonging to the control unit and controls activation of the selected activation target unit.Type: GrantFiled: December 20, 2010Date of Patent: February 11, 2014Assignee: Hitachi, Ltd.Inventor: Fumiaki Hosaka
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Patent number: 8438348Abstract: In control of the disk array device (backup system), when a blackout occurs, the disk array device is first operated in a first method to backed up a main memory by using a power supply from a battery. During the first method, a blackout continuous time and the like are integrated, and at a timing in which the integrated value satisfies a condition, the first method is then shifted to the second method to evacuate data from the main memory onto a nonvolatile memory based on a power supply.Type: GrantFiled: June 4, 2008Date of Patent: May 7, 2013Assignee: Hitachi, Ltd.Inventor: Fumiaki Hosaka
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Publication number: 20130047030Abstract: The supply of power to a storage apparatus can be made redundant by means of power inputs from two types of power supply, namely an AC power supply and a DC power supply. The storage apparatus comprises a power supply unit for supplying power to a plurality of storage devices, and a power supply controller for controlling a method of supplying power from the power supply unit, wherein the power supply unit makes redundant the power supplied from a first power supply device which supplies AC power and/or from a second power supply device which supplies DC power, and supplies this power to the plurality of storage devices, and wherein, in response to an operator configuration input, the power supply controller supplies power from the first power supply device to one storage device among the plurality of storage devices and supplies power from the second power supply device to another storage device.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Inventors: Tomonori Soeda, Hiroshi Suzuki, Fumiaki Hosaka, Toshimitsu Shishido
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Publication number: 20120246398Abstract: To shorten the time from power restoration to the resumption of business operation. During a power failure, a memory controller saves configuration information and directory information of a shared memory to a nonvolatile memory, and saves data of a cache memory to the nonvolatile memory. During power restoration from a power failure, the memory controller returns information of the nonvolatile memory to the shared memory so that it can be updated before the lapse of the initialization time, the micro processor executes online processing based on information of the shared memory, and the memory controller 70 controls the storage area of the cache memory so that it will become gradually writable according to the battery capacity of the battery if the battery capacity of the battery is still gradually increasing even after the lapse of the initialization time.Type: ApplicationFiled: June 11, 2012Publication date: September 27, 2012Applicant: HITACHI, LTD.Inventor: Fumiaki HOSAKA
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Patent number: 8214689Abstract: To shorten the time from power restoration to the resumption of business operation. During a power failure, a memory controller saves configuration information and directory information of a shared memory to a nonvolatile memory, and saves data of a cache memory to the nonvolatile memory. During power restoration from a power failure, the memory controller returns information of the nonvolatile memory to the shared memory so that it can be updated before the lapse of the initialization time, the micro processor executes online processing based on information of the shared memory, and the memory controller 70 controls the storage area of the cache memory so that it will become gradually writable according to the battery capacity of the battery if the battery capacity of the battery is still gradually increasing even after the lapse of the initialization time.Type: GrantFiled: February 19, 2010Date of Patent: July 3, 2012Assignee: Hitachi, Ltd.Inventor: Fumiaki Hosaka
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Publication number: 20120159210Abstract: The charge capacity of a battery for supplying electric power to a volatile memory and a non-volatile memory is increased without increasing the power source capacity. A control unit for controlling data input/output processing on a storage device is configured by combining a plurality of units which become load on a power source; and at the time of power interruption of a power source, the control unit saves data and information, which are stored in a volatile memory, to a nonvolatile memory. A battery charged by the power source supplies electric power to the volatile memory and the nonvolatile memory at the time of the power interruption. When the electric power is supplied from the power source to the control unit at the time of power recovery after the power interruption, a main controller selects an activation target unit, which is to be activated, from among the plurality of units belonging to the control unit and controls activation of the selected activation target unit.Type: ApplicationFiled: December 20, 2010Publication date: June 21, 2012Inventor: Fumiaki Hosaka
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Publication number: 20110208998Abstract: To shorten the time from power restoration to the resumption of business operation. During a power failure, a memory controller saves configuration information and directory information of a shared memory to a nonvolatile memory, and saves data of a cache memory to the nonvolatile memory. During power restoration from a power failure, the memory controller returns information of the nonvolatile memory to the shared memory so that it can be updated before the lapse of the initialization time, the micro processor executes online processing based on information of the shared memory, and the memory controller 70 controls the storage area of the cache memory so that it will become gradually writable according to the battery capacity of the battery if the battery capacity of the battery is still gradually increasing even after the lapse of the initialization time.Type: ApplicationFiled: February 19, 2010Publication date: August 25, 2011Applicant: HITACHI, LTD.Inventor: Fumiaki Hosaka
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Publication number: 20090249008Abstract: In control of the disk array device (backup system), when a blackout occurs, the disk array device is first operated in a first method to backed up a main memory by using a power supply from a battery. During the first method, a blackout continuous time and the like are integrated, and at a timing in which the integrated value satisfies a condition, the first method is then shifted to the second method to evacuate data from the main memory onto a nonvolatile memory based on a power supply.Type: ApplicationFiled: June 4, 2008Publication date: October 1, 2009Inventor: Fumiaki Hosaka