Patents by Inventor Fumiaki Okazaki

Fumiaki Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200066863
    Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Applicant: Sony Corporation
    Inventor: Fumiaki Okazaki
  • Patent number: 10505008
    Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 10, 2019
    Assignee: SONY CORPORATION
    Inventor: Fumiaki Okazaki
  • Publication number: 20180269300
    Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: Sony Corporation
    Inventor: Fumiaki Okazaki
  • Patent number: 10014384
    Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 3, 2018
    Assignee: SONY CORPORATION
    Inventor: Fumiaki Okazaki
  • Publication number: 20150084105
    Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Inventor: Fumiaki Okazaki
  • Patent number: 8817164
    Abstract: An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: August 26, 2014
    Assignee: Sony Corporation
    Inventors: Hiroshi Tayanaka, Susumu Ooki, Junichi Furukawa, Fumiaki Okazaki
  • Publication number: 20130292748
    Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.
    Type: Application
    Filed: June 12, 2013
    Publication date: November 7, 2013
    Inventor: Fumiaki Okazaki
  • Publication number: 20130234220
    Abstract: An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.
    Type: Application
    Filed: January 31, 2013
    Publication date: September 12, 2013
    Applicant: SONY CORPORATION
    Inventors: Hiroshi Tayanaka, Susumu Ooki, Junichi Furukawa, Fumiaki Okazaki
  • Patent number: 8486789
    Abstract: Disclosed herein is a method for manufacturing an insulated gate field effect transistor, the method including the steps of: (a) preparing a base that includes source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) forming a gate electrode by burying a conductive material layer in the gate electrode formation opening; (c) removing the insulating layer; and (d) depositing a first interlayer insulating layer and a second interlayer insulating layer sequentially across an entire surface, wherein in the step (d), the first interlayer insulating layer is deposited in a deposition atmosphere containing no oxygen atom.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: July 16, 2013
    Assignee: Sony Corporation
    Inventor: Fumiaki Okazaki
  • Patent number: 8390726
    Abstract: An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: March 5, 2013
    Assignee: Sony Corporation
    Inventors: Hiroshi Tayanaka, Susumu Ooki, Junichi Furukawa, Fumiaki Okazaki
  • Publication number: 20100245648
    Abstract: An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 30, 2010
    Applicant: SONY CORPORATION
    Inventors: Hiroshi Tayanaka, Susumu Ooki, Junichi Furukawa, Fumiaki Okazaki
  • Publication number: 20080197426
    Abstract: Disclosed herein is a method for manufacturing an insulated gate field effect transistor, the method including the steps of: (a) preparing a base that includes source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) forming a gate electrode by burying a conductive material layer in the gate electrode formation opening; (c) removing the insulating layer; and (d) depositing a first interlayer insulating layer and a second interlayer insulating layer sequentially across an entire surface, wherein in the step (d), the first interlayer insulating layer is deposited in a deposition atmosphere containing no oxygen atom.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 21, 2008
    Applicant: SONY CORPORATION
    Inventor: Fumiaki Okazaki