Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.

Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.

Abstract: An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.

Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.

Abstract: An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.

Abstract: Disclosed herein is a method for manufacturing an insulated gate field effect transistor, the method including the steps of: (a) preparing a base that includes source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) forming a gate electrode by burying a conductive material layer in the gate electrode formation opening; (c) removing the insulating layer; and (d) depositing a first interlayer insulating layer and a second interlayer insulating layer sequentially across an entire surface, wherein in the step (d), the first interlayer insulating layer is deposited in a deposition atmosphere containing no oxygen atom.

Abstract: An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.

Abstract: An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.

Abstract: Disclosed herein is a method for manufacturing an insulated gate field effect transistor, the method including the steps of: (a) preparing a base that includes source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) forming a gate electrode by burying a conductive material layer in the gate electrode formation opening; (c) removing the insulating layer; and (d) depositing a first interlayer insulating layer and a second interlayer insulating layer sequentially across an entire surface, wherein in the step (d), the first interlayer insulating layer is deposited in a deposition atmosphere containing no oxygen atom.