Patents by Inventor Fumiaki Yamana

Fumiaki Yamana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9535492
    Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to: determine whether or not a difference between a total of power consumption values of physical or virtual computers and a preset upper-limit value satisfies a certain condition; select, in ascending order of priorities stored in a first storage and set based on details of processing executed by the computers, any of the computers as a target whose power consumption is to be reduced, when the difference satisfies the certain condition; and switch the computer selected to a state in which the power consumption is reduced.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: January 3, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Fumiaki Yamana, Hiroshi Kondou, Kenji Gotsubo
  • Patent number: 9122597
    Abstract: Disclosed is an information processing device provided with: a plurality of processing units each having a TLB (Translation Lookaside Buffer); a means for acquiring a designation of a processing unit, from among the plurality of processing units, where TLB information is to be collected, and for acquiring a designation of the timing at which the TLB information is to be collected; and a means for collecting the TLB information from the designated processing unit at the designated timing.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 1, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Takafumi Anraku, Fumiaki Yamana, Hiroshi Kondou
  • Publication number: 20140181359
    Abstract: An information processing apparatus running multiple virtual machines includes a correspondence information storage section configured to store correspondence information between a virtual address and a physical address, the correspondence information being used by a second virtual machine when executing a procedure relevant to a first virtual machine; a correspondence information processing section configured to invalidate the correspondence information in response to an occurrence of a panic in the first virtual machine; and a preservation section configured to preserve content of a memory area allocated to the second virtual machine into a storage device.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Xiaoyang ZHANG, Fumiaki YAMANA, Kenji GOTSUBO, Hiroyuki IZUI
  • Publication number: 20130268791
    Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to: determine whether or not a difference between a total of power consumption values of physical or virtual computers and a preset upper-limit value satisfies a certain condition; select, in ascending order of priorities stored in a first storage and set based on details of processing executed by the computers, any of the computers as a target whose power consumption is to be reduced, when the difference satisfies the certain condition; and switch the computer selected to a state in which the power consumption is reduced.
    Type: Application
    Filed: April 3, 2013
    Publication date: October 10, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Fumiaki YAMANA, Hiroshi KONDOU, Kenji GOTSUBO
  • Publication number: 20120331266
    Abstract: Disclosed is an information processing device provided with: a plurality of processing units each having a TLB (Translation Lookaside Buffer); a means for acquiring a designation of a processing unit, from among the plurality of processing units, where TLB information is to be collected, and for acquiring a designation of the timing at which the TLB information is to be collected; and a means for collecting the TLB information from the designated processing unit at the designated timing.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Takafumi ANRAKU, Fumiaki Yamana, Hiroshi Kondou