Abstract: A semiconductor switch circuit comprises: a first switch pair including two MOSFETs having gates connected one another and sources connected to one another, and a zener diode reversely connected between the gates and sources of the MOSFETs; a second switch pair including two MOSFETs having gates connected one another and sources connected to one another, and a zener diode reversely connected between the gates and sources of the MOSFETs; and a third switch pair comprising two MOSFETs having gates connected to one another and sources connected to one another. The first switch pair and the second switch pair are connected in series between two input/output terminals through a connecting node. The third switch pair is connected to the connecting node between the first switch pair and the second switch pair.

Abstract: A semiconductor switch circuit comprises: a first switch pair including two MOSFETs having gates connected one another and sources connected to one another, and a zener diode reversely connected between the gates and sources of the MOSFETs; a second switch pair including two MOSFETs having gates connected one another and sources connected to one another, and a zener diode reversely connected between the gates and sources of the MOSFETs; and a third switch pair comprising two MOSFETs having gates connected to one another and sources connected to one another. The first switch pair and the second switch pair are connected in series between two input/output terminals through a connecting node. The third switch pair is connected to the connecting node between the first switch pair and the second switch pair.

Abstract: A debugging system has a central processing unit, a register group, a tracer and a trace buffer integrated on a single semiconductor chip, a main memory for storing a target program and other data and an emulator, and the tracer is connected to a cache memory of the central processing unit and the register group through built-in signal lines patterned over the semiconductor chip so that the tracer is responsive to a high-speed data processing of the central processing unit by virtue of the built-in signal lines merely coupled with small parasitic capacitors.

Abstract: An integrated circuit device sending trace data generated by a central processing unit (CPU) to a debug device without loss and a method of controlling the operation of the integrated circuit device. The integrated circuit device has the CPU executing various types of data processing. A trace buffer is connected via a parallel bus to a predetermined output terminal of the CPU. A buffer monitoring circuit is connected to an input terminal of the trace buffer and to a predetermined control terminal of the CPU. The CPU executes various types of data processing requested by a program and outputs trace data indicating an execution history. The trace buffer temporarily stores the trace data that is output in parallel by the CPU. When a usage amount of the trace buffer exceeds a preset threshold, the buffer monitoring circuit sends an interrupt signal BRKINT to the CPU to suspend the data processing of the CPU and, when a preset period of time elapses, releases the suspension of data processing of the CPU.

Abstract: An integrated circuit device sending trace data generated by a central processing unit (CPU) to a debug device without loss and a method of controlling the operation of the integrated circuit device. The integrated circuit device has the CPU executing various types of data processing. A trace buffer is connected via a parallel bus to a predetermined output terminal of the CPU. A buffer monitoring circuit is connected to an input terminal of the trace buffer and to a predetermined control terminal of the CPU. The CPU executes various types of data processing requested by a program and outputs trace data indicating an execution history. The trace buffer temporarily stores the trace data that is output in parallel by the CPU. When a usage amount of the trace buffer exceeds a preset threshold, the buffer monitoring circuit sends an interrupt signal BRKINT to the CPU to suspend the data processing of the CPU and, when a preset period of time elapses, releases the suspension of data processing of the CPU.

Abstract: While shortening a trace processing time duration of checking a target program, the target program is simply checked in a high speed. When historical data acquired by executing this target program is supplied, the historical data is converted into trace packet data. The trace packet data is temporarily stored into a trace packet buffer. When the storage content of the trace packet buffer is brought into an overflow state, the trace packet data and store-impossible data are stored into an external storage apparatus.