Abstract: Functional information acquired before and after an event occurrence is held on an on-chip MRAM built in a data processor, thus preventing the held functional information from being falsified and erased. An automobile recorder of the present invention comprises a one-chip data processor coupled to signal lines transmitting functional information indicating vehicle conditions and an external memory. The data processor comprises an input circuit which takes input of functional information, an MRAM for temporarily storing functional information, and a central processing unit (CPU). The CPU performs wrap-around control for storing functional information into the MRAM. The CPU also performs disabling control for disabling storing of functional information when the amount of new information being stored on the MRAM by wrap-around control in response to and following a certain event occurrence has reached a specific quantity that is less than a storage capacity from the initial address to the end address.

Abstract: A disconnection detecting circuit includes switches for setting a detection signal to be supplied for a signal line, a resistor for supplying the signal line with the detection signal set by the switches and control means for controlling the switches to set the detection signal to be supplied for the signal line and judging whether there is disconnection or not in the signal line on the basis of a change in the detection signal.

Abstract: A disconnection detecting circuit includes switches for setting a detection signal to be supplied for a signal line, a resistor for supplying the signal line with the detection signal set by the switches and control means for controlling the switches to set the detection signal to be supplied for the signal line and judging whether there is disconnection or not in the signal line on the basis of a change in the detection signal.

Abstract: An input bit string is latched sequentially by a D latch initialized to the logical level “1” and a plurality of D latches initialized to logical level “0”. If the data bit released from the last D latch, of the plurality of D latches, has a logical level “1”, a detection enabling circuit continuously keeps outputting a signal having a logical level “1”. This detection enabling circuit comprises an OR gate and another D latch. If the signal output by the detection enabling circuit has a logical level “1” and the bit pattern held in all of the D latches is “11111”, then an AND gate outputs a bit string detection signal having a logical level “1”.

Abstract: A watch dog timer (20) is controlled to permit or inhibit operation of a free run counter (3). When a flip-flop (14) is reset by a reset signal, no clock signal is supplied to the free run counter (3), the operation of which is then inhibited. When a microcomputer (1) outputs an address signal (5) and a write signal (6), an address decoder (12) decodes the address signal to open an AND gate (13), thereby to set the flip-flop (14). When the flip-flop (14) is set, and AND gate (17) is opened to supply clock pulses to the free run counter (3), which in turn starts counting the clock pulses. When the microcomputer (1) operates abnormally and no clear signal is supplied to the free run counter (3) from a clear decision circuit (2), the free run counter (3) outputs a signal indicating abnormal operation of the microcomputer (1) upon counting a prescribed counter value.