Patents by Inventor Fumihiko Ando
Fumihiko Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096914Abstract: Provided is an imaging element including a photoelectric conversion unit formed by stacking a first electrode, a photoelectric conversion layer and a second electrode. The photoelectric conversion unit further includes a charge storage electrode which is disposed to be spaced apart from the first electrode and disposed opposite to the photoelectric conversion layer via an insulating layer. The photoelectric conversion unit is formed of N number of photoelectric conversion unit segments, and the same applies to the photoelectric conversion layer, the insulating layer and the charge storage electrode. An nth photoelectric conversion unit segment is formed of an nth charge storage electrode segment, an nth insulating layer segment and an nth photoelectric conversion layer segment. As n increases, the nth photoelectric conversion unit segment is located farther from the first electrode. A thickness of the insulating layer segment gradually changes from a first to Nth photoelectric conversion unit segment.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: SONY GROUP CORPORATIONInventors: Akira FURUKAWA, Yoshihiro ANDO, Hideaki TOGASHI, Fumihiko KOGA
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Patent number: 11936744Abstract: According to one embodiment, a client system includes a system controller and a unit. The unit has a function of acquiring or creating information. And the system controller acquires and manages the information from the unit. The system controller may classify the unit into a section to be managed, and hold the information regarding the section to which the unit belong.Type: GrantFiled: April 14, 2020Date of Patent: March 19, 2024Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hideo Ando, Fumihiko Murakami, Takumi Hara
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Publication number: 20210185936Abstract: A plant cultivation device and the like capable of growing a plant while preventing leaves thereof from curling are provided. The device includes: a first illumination irradiating the plant to be cultivated with blue light; a second illumination irradiating the plant with red light; and a controller controlling irradiation of the blue light from the first illumination and irradiation of the red light from the second illumination, wherein the controller controls the blue light irradiation to be performed 21 hours or more a day including a case in which the blue light irradiation is performed 5 hours or more without performing the red light irradiation, and the red light irradiation to be performed 12 hours or more a day.Type: ApplicationFiled: October 26, 2020Publication date: June 24, 2021Applicant: SHOWA DENKO K.K.Inventors: Fumihiko ANDO, Yao JU, Noriko OHTAKE, Shinji YAMAKI, Masaharu ISHIKURA
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Patent number: 6621169Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: GrantFiled: August 29, 2001Date of Patent: September 16, 2003Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
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Patent number: 6564987Abstract: A method of evaluating configuration of solder external terminals of a BGA-type tape-based semiconductor device mounted on a board such that the external terminals are joined to lands provided on the mounting board is provided. The method includes the step of obtaining geometric data related to opening of a tape substrate of the semiconductor device, solder balls to be placed at positions corresponding to the openings, and the lands of the mounting board and the step of deribing configuration of the solder external terminal based on the geometric date. The method further includes the step of calculating the volume of voids to be produced in the external terminals, so as to compensate for the geometric data related to the tape substrate.Type: GrantFiled: March 20, 2001Date of Patent: May 20, 2003Assignee: Fujitsu LimitedInventors: Kanako Imai, Nobutaka Ito, Fumihiko Ando
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Patent number: 6528348Abstract: A plurality of semiconductor devices can be mounted on a mounting board in a three-dimensional structure by stacking one on another with a simple structure. A semiconductor element is mounted on a first surface of an interposer. Electrode pads connected to the semiconductor element are arranged around the semiconductor element on the first surface of the interposer. Protruding electrodes are provided on the respective electrode pads. Through holes are formed in the interposer so as to extend from a second surface opposite to the first surface of the redistribution substrate to the respective electrode pads. The semiconductor element is encapsulated by a seal resin. Each of the protruding electrodes is higher than the sealed portion of the semiconductor element.Type: GrantFiled: February 19, 2002Date of Patent: March 4, 2003Assignee: Fujitsu LimitedInventors: Fumihiko Ando, Akira Takashima, Hiroshi Onodera, Eiji Yoshida, Kazuo Teshirogi
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Publication number: 20020084308Abstract: A method of evaluating configuration of solder external terminals of a BGA-type tape-based semiconductor device mounted on a board such that the external terminals are joined to lands provided on the mounting board is provided. The method includes the step of obtaining geometric data related to opening of a tape substrate of the semiconductor device, solder balls to be placed at positions corresponding to the openings, and the lands of the mounting board and the step of deribing configuration of the solder external terminal based on the geometric date. The method further includes the step of calculating the volume of voids to be produced in the external terminals, so as to compensate for the geometric data related to the tape substrate.Type: ApplicationFiled: March 20, 2001Publication date: July 4, 2002Applicant: Fujitsu Limited, Kawasaki, JapanInventors: Kanako Imai, Nobutaka Ito, Fumihiko Ando
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Publication number: 20020074630Abstract: A plurality of semiconductor devices can be mounted on a mounting board in a three-dimensional structure by stacking one on another with a simple structure. A semiconductor element is mounted on a first surface of an interposer. Electrode pads connected to the semiconductor element are arranged around the semiconductor element on the first surface of the interposer. Protruding electrodes are provided on the respective electrode pads. Through holes are formed in the interposer so as to extend from a second surface opposite to the first surface of the redistribution substrate to the respective electrode pads. The semiconductor element is encapsulated by a seal resin. Each of the protruding electrodes is higher than the sealed portion of the semiconductor element.Type: ApplicationFiled: February 19, 2002Publication date: June 20, 2002Applicant: FUJITSU LIMITEDInventors: Fumihiko Ando, Akira Takashima, Hiroshi Onodera, Eiji Yoshida, Kazuo Teshirogi
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Patent number: 6388333Abstract: A plurality of semiconductor devices can be mounted on a mounting board in a three-dimensional structure by stacking one on another with a simple structure. A semiconductor element is mounted on a first surface of an interposer. Electrode pads connected to the semiconductor element are arranged around the semiconductor element on the first surface of the interposer. Protruding electrodes are provided on the respective electrode pads. Through holes are formed in the interposer so as to extend from a second surface opposite to the first surface of the redistribution substrate to the respective electrode pads. The semiconductor element is encapsulated by a seal resin. Each of the protruding electrodes is higher than the sealed portion of the semiconductor element.Type: GrantFiled: June 27, 2000Date of Patent: May 14, 2002Assignee: Fujitsu LimitedInventors: Fumihiko Taniguchi, Kouhei Orikawa, Tadashi Uno, Fumihiko Ando, Akira Takashima, Hiroshi Onodera, Eiji Yoshida, Kazuo Teshirogi
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Publication number: 20020027295Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: ApplicationFiled: August 29, 2001Publication date: March 7, 2002Applicant: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
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Patent number: 6281571Abstract: External connection electrodes can be positively mounted on a substrate when the pitch between the external connection electrodes is reduced and the diameter of each through hole formed in the substrate is reduced. A semiconductor chip is mounted on a first surface of a tape substrate. Electrode films are formed on the first surface of the tape substrate, each of the electrode films electrically connected to the semiconductor chip. External connection electrodes are provided on a second surface of the tape substrate, each of the external connection electrodes connected to a respective one of the electrode films via a through hole formed in the tape substrate. The external connection electrodes are formed on the electrode films by plating. A diameter S1 of a portion of each of the external connection electrodes protruding from the second surface of the tape substrate and a diameter S2 of the through hole satisfy a relationship S1≦S2.Type: GrantFiled: March 24, 2000Date of Patent: August 28, 2001Assignee: Fujitsu LimitedInventors: Akira Takashima, Fumihiko Ando, Mitsuru Sato, Takashi Suzuki, Yoshikazu Kumagaya, Kazunari Kosakai
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Patent number: 5101255Abstract: Disclosed is a photoelectric conversion device which comprises: a photoconductive layer made of amorphous semiconductor material which shows charge multiplication and which converts photo signals into electric signals; and a substrate having electric circuits or the like (for example switching elements) for reading the electric signals. The amorphous semiconductor material used according to the invention shows the charge multiplication action under predetermined intensity of electric field so that a high sensitive photoelectric conversion device having a gain which is not smaller than 1 is realized.Type: GrantFiled: July 24, 1989Date of Patent: March 31, 1992Inventors: Sachio Ishioka, Yukio Takasaki, Tadaaki Hirai, Kazutaka Tsuji, Tatsuo Makishima, Yasuhiko Nonaka, Tatsuro Kawamura, Takashi Yamashita, Kazuhisa Taketoshi, Keiichi Shidara, Fumihiko Ando, Kenkichi Tanioka
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Patent number: 4839729Abstract: A solid state image sensor including a light receiving section having a number of light receiving cells arranged in matrix, and a reading and storing section having a first set of switching and memory transistors for reading bright signals read out of light receiving cells arranged in a row and storing the same for a horizontal scanning period, a second set of switching and memory transistors for reading dark signals out of light receiving cells arranged in a row and storing the same for a horizontal scanning period, and a set of reading transistors for reading the bright and dark signals simultaneously out of the first and second sets of memory transistors for respective pixels successively. The light receiving section and the reading and storing section are formed integrally in the same semiconductor substrate. In order to remove the fixed pattern noise, there is derived differences between the simultaneously readout bright and dark signals with the aid of a differential amplifier.Type: GrantFiled: April 26, 1988Date of Patent: June 13, 1989Assignees: Nippon Hoso Kyokai, Olympus Optical Co., Ltd.Inventors: Fumihiko Ando, Junji Kumada, Yoshihiro Fujita, Hidetoshi Yamada, Kazuhiko Nakamura
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Patent number: 4710817Abstract: A solid state image sensor comprising a plurality of photosensors (8A) including a plurality of avalanche photodiodes (12A) arranged at least in the form of a one-dimensional array and delivering pulse signals each representing the number of photons incident to each of the photosensors; counters (10A) connected to the respective photosensors (8A) to count the pulse signals and hold the count value as a video output; a reset circuit (5) for resetting the counters (10A) to the initial states at a predetermined frequency; and a scanning circuit (14) for sequentially reading out the count value in the counters (10A). The counter (10A) counts the number of photons subjected to photoelectric conversion by the photodiode (12A) so that the video signal is directly derived in the form of a digital signal and thus the video signal with a high S/N ratio is obtained.Type: GrantFiled: August 25, 1986Date of Patent: December 1, 1987Assignee: Nippon Hoso KyokaiInventor: Fumihiko Ando
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Patent number: 4525742Abstract: A two-dimensional solid-state image sensor device comprising a plurality of picture cells two-dimensionally arranged in column and row directions. Each cell has a static induction transistor having drain and source regions disposed on opposite sides of a high resistance semiconductor channel region, and a gate region adjacent to the channel region to control a current flowing between the drain and source regions, and a transparent electrode disposed via a capacitance on at least a portion of the gate region, in a manner that light is incident through the transparent electrode to the gate region in which the charge produced by the light excitation is stored to control the current. Selection lines connected to the gate regions in each column in common via the capacitances are sequentially selected.Type: GrantFiled: February 13, 1984Date of Patent: June 25, 1985Assignee: Fuji Photo Film Co. Ltd.Inventors: Junichi Nishizawa, Takashige Tamamushi, Fumihiko Ando, Shigeo Yoshikawa, Koji Shimanuki
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Patent number: 4363963Abstract: A solid state photo-electric converting device consists of a direct conjunction of a photo-electric converting layers formed of satisfactorily selected materials and a solid state amplifier formed, for instance, of an FET, a conductive electrode being inserted therebetween for collecting signal charges induced in those converting layers efficiently, thereby an excellent spectral sensitivity performance and an extremely high conversion efficiency being realizabe. Accordingly, a solid state imaging apparatus employing a matrix of the above converting devices can be provided with an excellent spectral and noiseless performance.Type: GrantFiled: February 26, 1980Date of Patent: December 14, 1982Assignee: Nippon Hoso KyokaiInventor: Fumihiko Ando