Patents by Inventor Fumihiko Nitta
Fumihiko Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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AUXILIARY POWER SUPPLY UNIT, METHOD FOR CONTROLLING AUXILIARY POWER SUPPLY UNIT, AND STEERING SYSTEM
Publication number: 20240124050Abstract: An auxiliary power supply unit includes an auxiliary power supply device and a downstream power supply line group connecting the auxiliary power supply device to motor units. The auxiliary power supply device includes: an auxiliary power supply provided on a power supply path; and a switching circuit configured to switch the connection state of the auxiliary power supply to the power supply path. The connection state of the auxiliary power supply includes a boost state in which the auxiliary power supply is connected in series with the external power supply. The downstream power supply line group includes branch first downstream drive lines and branch second downstream drive lines. Each of the upstream ends of the branch first downstream drive lines and the branch second downstream drive lines is connected to the power supply path at a position downstream of the auxiliary power supply.Type: ApplicationFiled: March 19, 2021Publication date: April 18, 2024Applicant: JTEKT CORPORATIONInventors: Tomonori TOTOUMI, Takumi MIO, Fumihiko SATO, Satoshi SHINODA, Hiroki NITTA, Kouhei OTA -
Patent number: 9208828Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.Type: GrantFiled: May 4, 2014Date of Patent: December 8, 2015Assignee: Renesas Electronics CorporationInventors: Satoru Hanzawa, Fumihiko Nitta, Nozomu Matsuzaki, Toshihiro Tanaka
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Patent number: 9129893Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.Type: GrantFiled: October 1, 2014Date of Patent: September 8, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Fumihiko Nitta
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Publication number: 20150014757Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.Type: ApplicationFiled: October 1, 2014Publication date: January 15, 2015Inventor: Fumihiko NITTA
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Patent number: 8866244Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.Type: GrantFiled: January 12, 2012Date of Patent: October 21, 2014Assignee: Renesas Electronics CorporationInventor: Fumihiko Nitta
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Publication number: 20140241051Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.Type: ApplicationFiled: May 4, 2014Publication date: August 28, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Satoru HANZAWA, Fumihiko NITTA, Nozomu MATSUZAKI, Toshihiro TANAKA
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Patent number: 8737116Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.Type: GrantFiled: June 25, 2013Date of Patent: May 27, 2014Assignee: Renesas Electronics CorporationInventors: Satoru Hanzawa, Fumihiko Nitta, Nozomu Matsuzaki, Toshihiro Tanaka
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Publication number: 20130277635Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.Type: ApplicationFiled: June 25, 2013Publication date: October 24, 2013Inventors: Satoru HANZAWA, Fumihiko NITTA, Nozomu MATSUZAKI, Toshihiro TANAKA
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Patent number: 8482961Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.Type: GrantFiled: April 25, 2012Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventors: Satoru Hanzawa, Fumihiko Nitta, Nozomu Matsuzaki, Toshihiro Tanaka
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Patent number: 8338817Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: GrantFiled: October 21, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
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Publication number: 20120268981Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.Type: ApplicationFiled: April 25, 2012Publication date: October 25, 2012Inventors: SATORU HANZAWA, Fumihiko Nitta, Nozomu Matsuzaki, Toshihiro Tanaka
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Publication number: 20120199895Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.Type: ApplicationFiled: January 12, 2012Publication date: August 9, 2012Inventor: Fumihiko Nitta
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Patent number: 8179739Abstract: A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.Type: GrantFiled: August 10, 2007Date of Patent: May 15, 2012Assignee: Renesas Electronics CorporationInventors: Satoru Hanzawa, Fumihiko Nitta, Nozomu Matsuzaki, Toshihiro Tanaka
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Publication number: 20120068282Abstract: To provide a semiconductor device capable of suppressing a short circuit between an upper conductive element and a lower conductive element which constitute an MRAM, and a manufacturing method of the same. There are provided a semiconductor substrate having a main surface, a magnetic tunnel junction structure located over the main surface of the semiconductor substrate and including a pin layer, a tunnel insulating layer, and a free layer, a lower insulating layer contacting a lower side surface of the magnetic tunnel junction structure, a sidewall insulating layer located over the lower insulating layer in contact with the upper side surface of the magnetic tunnel junction structure, and exposing the top surface of the magnetic tunnel junction structure, and a conductive layer contacting the top surface of the magnetic tunnel junction structure exposed from the sidewall insulating layer.Type: ApplicationFiled: July 22, 2011Publication date: March 22, 2012Inventors: Masamichi MATSUOKA, Tatsuya Fukumura, Fumihiko Nitta
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Publication number: 20120037874Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: ApplicationFiled: October 21, 2011Publication date: February 16, 2012Applicant: Renesas Electronics CorporationInventors: Masahiro MONIWA, Fumihiko NITTA, Masamichi MATSUOKA, Satoshi IIDA
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Patent number: 8071456Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: GrantFiled: August 27, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
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Publication number: 20110211390Abstract: A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.Type: ApplicationFiled: August 10, 2007Publication date: September 1, 2011Applicant: RENESAS TECHNOLOGY CROP.Inventors: Satoru Hanzawa, Fumihiko Nitta, Nozomu Matsuzaki, Toshihiro Tanaka
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Publication number: 20110080779Abstract: A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.Type: ApplicationFiled: December 15, 2010Publication date: April 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Fumihiko NITTA, Yoshikazu IIDA, Takashi YAMAKI
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Patent number: 7902539Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.Type: GrantFiled: November 20, 2008Date of Patent: March 8, 2011Assignee: Renesas Technology Corp.Inventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
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Patent number: 7881102Abstract: A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.Type: GrantFiled: February 12, 2009Date of Patent: February 1, 2011Assignee: Renesas Electronics CorporationInventors: Fumihiko Nitta, Yoshikazu Iida, Takashi Yamaki