Patents by Inventor Fumihiko Tajima

Fumihiko Tajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090140769
    Abstract: A System-in-Package includes a first chip to be mounted in common for a plurality of product types, a second chip having different specifications for each product type, and a wiring substrate being common to a plurality of product types, on which the first chip and the second chip are to be mounted. A setting signal is supplied from the second chip to the first chip.
    Type: Application
    Filed: November 5, 2008
    Publication date: June 4, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Katsunobu Suzuki, Takao Ikeuchi, Fumihiko Tajima, Kazuaki Maehara, Hajime Kawamura, Makoto Wakasugi
  • Patent number: 6075377
    Abstract: A connecting state of a signal terminal provided in a semiconductor device is confirmed by externally applying a voltage through a resistor to the signal terminal and detecting a voltage value range in which a voltage value measured at the signal terminal falls. Although the number of measurements of voltage value at the signal terminals to be tested is increased compared with the conventional method, the time necessary for each measurement is very short and it is possible to substantially reduce the total test time.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventor: Fumihiko Tajima
  • Patent number: 5939894
    Abstract: A CMOS integrated circuit is tested by creating a database in which types of CMOS functional units of the integrated circuit are mapped to values of quiescent power supply currents which would flow through the functional units corresponding to all possible internal states of the integrated circuit. A test pattern is applied to a simulation model of the functional units of the integrated circuits and an output is detected therefrom. Corresponding to the output of the simulation model, values of the quiescent power supply currents are read from the database and a decision threshold is derived from a total sum of the read values. A power supply current of the integrated circuit is then measured while subjecting it to the test pattern and the measured current is compared with the decision threshold to produce a test result of the integrated circuit.
    Type: Grant
    Filed: October 24, 1996
    Date of Patent: August 17, 1999
    Assignee: NEC Corporation
    Inventors: Hisashi Yamauchi, Fumihiko Tajima, Yoshiyuki Inomata