Patents by Inventor Fumihiko Terasaki
Fumihiko Terasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11079416Abstract: The present invention provides a voltage monitoring apparatus capable of stable operation even in a low-voltage region. The voltage monitoring apparatus (1) includes: an inner voltage generating portion (40), lowering an input voltage (VIN) to generate an inner voltage (Vreg); an input voltage monitoring portion (30), receiving a power supply from an output terminal of the inner voltage generating portion (40) to operate; a switch portion (50), disposed between an input terminal of the input voltage (VIN) and the output terminal of the inner voltage generating portion (40); and a switch driving portion (60), turning on the switch portion (50) when the input voltage (VIN) is lower than a threshold voltage (for example, Vy<Vref), and turning off the switch portion (50) when the input voltage (VIN) is higher than the threshold voltage (for example, Vy>Vref).Type: GrantFiled: April 9, 2020Date of Patent: August 3, 2021Assignee: Rohm Co., Ltd.Inventor: Fumihiko Terasaki
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Publication number: 20200326359Abstract: The present invention provides a voltage monitoring apparatus capable of stable operation even in a low-voltage region. The voltage monitoring apparatus (1) includes: an inner voltage generating portion (40), lowering an input voltage (VIN) to generate an inner voltage (Vreg); an input voltage monitoring portion (30), receiving a power supply from an output terminal of the inner voltage generating portion (40) to operate; a switch portion (50), disposed between an input terminal of the input voltage (VIN) and the output terminal of the inner voltage generating portion (40); and a switch driving portion (60), turning on the switch portion (50) when the input voltage (VIN) is lower than a threshold voltage (for example, Vy<Vref), and turning off the switch portion (50) when the input voltage (VIN) is higher than the threshold voltage (for example, Vy>Vref).Type: ApplicationFiled: April 9, 2020Publication date: October 15, 2020Applicant: ROHM CO., LTD.Inventor: Fumihiko Terasaki
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Patent number: 10591947Abstract: Power supply voltage monitoring circuit includes: input terminal; output terminal; ground terminal; voltage dividing circuit generating first and second divided voltages from power supply voltage applied to the input terminal; reference voltage source generating reference voltage using the power supply voltage; regulator voltage source generating regulator voltage higher than the reference voltage using the power supply voltage; comparator generating first binary output signal by comparing the reference voltage with the first divided voltage, using the regulator voltage as driving source; first switching part having main conductive path connected between the output terminal and the ground terminal and responsive to the first binary output signal; and second binary converting part generating second binary output signal in response to the second divided voltage, using the reference voltage as driving source, wherein binary power supply voltage monitoring output signal is generated according to logical operationType: GrantFiled: April 2, 2019Date of Patent: March 17, 2020Assignee: Rohm Co., Ltd.Inventor: Fumihiko Terasaki
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Publication number: 20190310677Abstract: Power supply voltage monitoring circuit includes: input terminal; output terminal; ground terminal; voltage dividing circuit generating first and second divided voltages from power supply voltage applied to the input terminal; reference voltage source generating reference voltage using the power supply voltage; regulator voltage source generating regulator voltage higher than the reference voltage using the power supply voltage; comparator generating first binary output signal by comparing the reference voltage with the first divided voltage, using the regulator voltage as driving source; first switching part having main conductive path connected between the output terminal and the ground terminal and responsive to the first binary output signal; and second binary converting part generating second binary output signal in response to the second divided voltage, using the reference voltage as driving source, wherein binary power supply voltage monitoring output signal is generated according to logical operationType: ApplicationFiled: April 2, 2019Publication date: October 10, 2019Applicant: Rohm Co., Ltd.Inventor: Fumihiko Terasaki
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Patent number: 9148917Abstract: A load driving device includes a switch element configured to generate an output voltage to a load from an input voltage depending on an ON/OFF operation thereof, a switch controller configured to control the ON/OFF operation of the switch element such that a feedback voltage obtained by subtracting a dropped voltage of the load from the output voltage and a predetermined reference voltage are maintained to be consistent, and a variable current source configured to perform ON/OFF controlling of a driving current flowing to the load in response to a driving current control signal. When the switch element is in an ON state at an OFF timing of the driving current, the switch controller maintains the switch element in the ON state thereafter, and turns off the switch element when the ON period of the switch element reaches a predetermined period.Type: GrantFiled: January 20, 2012Date of Patent: September 29, 2015Assignee: Rohm Co., Ltd.Inventors: Masaki Omi, Fumihiko Terasaki
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Patent number: 8304885Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.Type: GrantFiled: December 28, 2010Date of Patent: November 6, 2012Assignee: Rohm Co., Ltd.Inventor: Fumihiko Terasaki
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Publication number: 20120187858Abstract: A load driving device includes a switch element configured to generate an output voltage to a load from an input voltage depending on an ON/OFF operation thereof, a switch controller configured to control the ON/OFF operation of the switch element such that a feedback voltage obtained by subtracting a dropped voltage of the load from the output voltage and a predetermined reference voltage are maintained to be consistent, and a variable current source configured to perform ON/OFF controlling of a driving current flowing to the load in response to a driving current control signal. When the switch element is in an ON state at an OFF timing of the driving current, the switch controller maintains the switch element in the ON state thereafter, and turns off the switch element when the ON period of the switch element reaches a predetermined period.Type: ApplicationFiled: January 20, 2012Publication date: July 26, 2012Applicant: ROHM CO., LTD.Inventors: Masaki Omi, Fumihiko Terasaki
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Patent number: 7944040Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.Type: GrantFiled: March 26, 2010Date of Patent: May 17, 2011Assignee: Rohm Co., LtdInventor: Fumihiko Terasaki
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Publication number: 20110089565Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.Type: ApplicationFiled: December 28, 2010Publication date: April 21, 2011Applicant: ROHM CO., LTD.Inventor: Fumihiko TERASAKI
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Publication number: 20100181668Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.Type: ApplicationFiled: March 26, 2010Publication date: July 22, 2010Applicant: ROHM CO., LTD.Inventor: Fumihiko TERASAKI
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Patent number: 7719107Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.Type: GrantFiled: September 23, 2004Date of Patent: May 18, 2010Assignee: Rohm Co., Ltd.Inventor: Fumihiko Terasaki
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Publication number: 20050067696Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.Type: ApplicationFiled: September 23, 2004Publication date: March 31, 2005Inventor: Fumihiko Terasaki