Patents by Inventor Fumihiko Terasaki

Fumihiko Terasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11079416
    Abstract: The present invention provides a voltage monitoring apparatus capable of stable operation even in a low-voltage region. The voltage monitoring apparatus (1) includes: an inner voltage generating portion (40), lowering an input voltage (VIN) to generate an inner voltage (Vreg); an input voltage monitoring portion (30), receiving a power supply from an output terminal of the inner voltage generating portion (40) to operate; a switch portion (50), disposed between an input terminal of the input voltage (VIN) and the output terminal of the inner voltage generating portion (40); and a switch driving portion (60), turning on the switch portion (50) when the input voltage (VIN) is lower than a threshold voltage (for example, Vy<Vref), and turning off the switch portion (50) when the input voltage (VIN) is higher than the threshold voltage (for example, Vy>Vref).
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 3, 2021
    Assignee: Rohm Co., Ltd.
    Inventor: Fumihiko Terasaki
  • Publication number: 20200326359
    Abstract: The present invention provides a voltage monitoring apparatus capable of stable operation even in a low-voltage region. The voltage monitoring apparatus (1) includes: an inner voltage generating portion (40), lowering an input voltage (VIN) to generate an inner voltage (Vreg); an input voltage monitoring portion (30), receiving a power supply from an output terminal of the inner voltage generating portion (40) to operate; a switch portion (50), disposed between an input terminal of the input voltage (VIN) and the output terminal of the inner voltage generating portion (40); and a switch driving portion (60), turning on the switch portion (50) when the input voltage (VIN) is lower than a threshold voltage (for example, Vy<Vref), and turning off the switch portion (50) when the input voltage (VIN) is higher than the threshold voltage (for example, Vy>Vref).
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Applicant: ROHM CO., LTD.
    Inventor: Fumihiko Terasaki
  • Patent number: 10591947
    Abstract: Power supply voltage monitoring circuit includes: input terminal; output terminal; ground terminal; voltage dividing circuit generating first and second divided voltages from power supply voltage applied to the input terminal; reference voltage source generating reference voltage using the power supply voltage; regulator voltage source generating regulator voltage higher than the reference voltage using the power supply voltage; comparator generating first binary output signal by comparing the reference voltage with the first divided voltage, using the regulator voltage as driving source; first switching part having main conductive path connected between the output terminal and the ground terminal and responsive to the first binary output signal; and second binary converting part generating second binary output signal in response to the second divided voltage, using the reference voltage as driving source, wherein binary power supply voltage monitoring output signal is generated according to logical operation
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: March 17, 2020
    Assignee: Rohm Co., Ltd.
    Inventor: Fumihiko Terasaki
  • Publication number: 20190310677
    Abstract: Power supply voltage monitoring circuit includes: input terminal; output terminal; ground terminal; voltage dividing circuit generating first and second divided voltages from power supply voltage applied to the input terminal; reference voltage source generating reference voltage using the power supply voltage; regulator voltage source generating regulator voltage higher than the reference voltage using the power supply voltage; comparator generating first binary output signal by comparing the reference voltage with the first divided voltage, using the regulator voltage as driving source; first switching part having main conductive path connected between the output terminal and the ground terminal and responsive to the first binary output signal; and second binary converting part generating second binary output signal in response to the second divided voltage, using the reference voltage as driving source, wherein binary power supply voltage monitoring output signal is generated according to logical operation
    Type: Application
    Filed: April 2, 2019
    Publication date: October 10, 2019
    Applicant: Rohm Co., Ltd.
    Inventor: Fumihiko Terasaki
  • Patent number: 9148917
    Abstract: A load driving device includes a switch element configured to generate an output voltage to a load from an input voltage depending on an ON/OFF operation thereof, a switch controller configured to control the ON/OFF operation of the switch element such that a feedback voltage obtained by subtracting a dropped voltage of the load from the output voltage and a predetermined reference voltage are maintained to be consistent, and a variable current source configured to perform ON/OFF controlling of a driving current flowing to the load in response to a driving current control signal. When the switch element is in an ON state at an OFF timing of the driving current, the switch controller maintains the switch element in the ON state thereafter, and turns off the switch element when the ON period of the switch element reaches a predetermined period.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: September 29, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Masaki Omi, Fumihiko Terasaki
  • Patent number: 8304885
    Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: November 6, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Fumihiko Terasaki
  • Publication number: 20120187858
    Abstract: A load driving device includes a switch element configured to generate an output voltage to a load from an input voltage depending on an ON/OFF operation thereof, a switch controller configured to control the ON/OFF operation of the switch element such that a feedback voltage obtained by subtracting a dropped voltage of the load from the output voltage and a predetermined reference voltage are maintained to be consistent, and a variable current source configured to perform ON/OFF controlling of a driving current flowing to the load in response to a driving current control signal. When the switch element is in an ON state at an OFF timing of the driving current, the switch controller maintains the switch element in the ON state thereafter, and turns off the switch element when the ON period of the switch element reaches a predetermined period.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 26, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Masaki Omi, Fumihiko Terasaki
  • Patent number: 7944040
    Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: May 17, 2011
    Assignee: Rohm Co., Ltd
    Inventor: Fumihiko Terasaki
  • Publication number: 20110089565
    Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.
    Type: Application
    Filed: December 28, 2010
    Publication date: April 21, 2011
    Applicant: ROHM CO., LTD.
    Inventor: Fumihiko TERASAKI
  • Publication number: 20100181668
    Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.
    Type: Application
    Filed: March 26, 2010
    Publication date: July 22, 2010
    Applicant: ROHM CO., LTD.
    Inventor: Fumihiko TERASAKI
  • Patent number: 7719107
    Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: May 18, 2010
    Assignee: Rohm Co., Ltd.
    Inventor: Fumihiko Terasaki
  • Publication number: 20050067696
    Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.
    Type: Application
    Filed: September 23, 2004
    Publication date: March 31, 2005
    Inventor: Fumihiko Terasaki