Patents by Inventor Fumihiko Uchida

Fumihiko Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100131093
    Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
    Type: Application
    Filed: September 9, 2009
    Publication date: May 27, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Natsuki YOKOYAMA, Yoshifumi KAWAMOTO, Eiichi MURAKAMI, Fumihiko UCHIDA, Kenichi MIZUISHI, Yoshio KAWAMURA
  • Patent number: 7603194
    Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: October 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20080243293
    Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
    Type: Application
    Filed: May 28, 2008
    Publication date: October 2, 2008
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 7392106
    Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: June 24, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 7310563
    Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 18, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 7062344
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 13, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20060111805
    Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 25, 2006
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20060111802
    Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 25, 2006
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20040107020
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Application
    Filed: November 17, 2003
    Publication date: June 3, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 6099598
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: August 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 5981399
    Abstract: A semiconductor device fabrication apparatus having multiple processing chambers for different processes, where a substrate is carried in and out in a sophisticated manner, with their different internal ambient conditions being retained, so that the substrate is free from contamination, thereby manufacturing high-quality semiconductor devices at high throughput. The apparatus includes a movable buffer chamber having a wafer carriage means within a transfer chamber which faces a process chamber, an evacuation means which evacuates of gas the buffer chamber, transfer chamber and process chamber independently, a gas feed means, and a control means.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: November 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Kawamura, Tatuharu Yamamoto, Shigeo Moriyama, Yoshifumi Kawamoto, Natsuki Yokoyama, Fumihiko Uchida, Minoru Hidaka, Miyako Matsui
  • Patent number: 5858863
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: January 12, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 5820679
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: October 13, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 5689494
    Abstract: A fine-fabrication method of solid surfaces relates to a new surface fabrication method allows a solid-device surface to be fabricated at an atomic scale so as to produce an ultra-fine device or a device for recording information at an ultra-high density. A probe is installed with a tip thereof facing to the surface of a specimen to undergo fabrication. A voltage for forming an electric field is applied between the probe and the specimen. The electric field is large enough to field-evaporate atoms constituting the specimen or the probe; the electric field field-evaporates atoms constituting the specimen, removing them from the surface of the specimen; and as another alternative, the electric field field-evaporates atoms constituting the probe, depositing them on the surface of the specimen.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: November 18, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Ichikawa, Shigeyuki Hosoki, Fumihiko Uchida, Shigeo Kato, Yoshihisa Fujisaki, Sumiko Fujisaki, Atsushi Kikugawa, Ryo Imura, Hajime Aoi, Kiyokazu Nakagawa, Eiichi Murakami
  • Patent number: 5628828
    Abstract: Process equipment and method for processing a semiconductor device comprising a buffer chamber, at least one process chamber connected to the buffer chamber through an opening portion, a holding/carrying unit disposed at a position facing the opening portion for holding and carrying a member to be processed such as a wafer, and a carrier unit disposed in the buffer chamber for transferring the member to be processed to and from the holding/carrying unit. The holding/carrying unit includes a flattened surface closely facing the opening portion for holding an atmosphere in the at least one process chamber independently from an atmosphere in the buffer chamber. The opening portion has a flattened surface closely facing the flattened surface of the holding/carrying unit.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: May 13, 1997
    Assignee: Hitachi , Ltd.
    Inventors: Yoshio Kawamura, Shigeo Moriyama, Tatuharu Yamamoto, Fumihiko Uchida
  • Patent number: 5601686
    Abstract: A wafer transport method including the steps of preparing a semiconductor process equipment having a transport chamber, a process chamber, an interface means for connecting the transport chamber to the process chamber, and a transport means for transporting a semiconductor wafer from the transport chamber to the process chamber by way of the interface means; inserting the transport means mounting a substrate in a communicating corridor including a supply means and an exhaust means; and transporting the substrate while performing the supply and exhaust by sequentially controlling a supply shutoff means, an exhaust shutoff means, and a communicating shutoff means according to the position of a conductance part formed of a gap between the transport means and the communicating corridor.
    Type: Grant
    Filed: May 3, 1996
    Date of Patent: February 11, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Kawamura, Yoshifumi Kawamoto, Fumihiko Uchida, Kenichi Mizuishi, Natsuki Yokoyama, Eiichi Murakami, Yoshinori Nakayama, Eiichi Seya
  • Patent number: 5562800
    Abstract: A wafer transport method includes the steps of preparing a semiconductor process equipment having a transport chamber and a process chamber. An interface means connects the transport chamber to the process chamber. A transport means transports a semiconductor wafer from the transport chamber to the process chamber by way of the interface means. The transport means mounting a substrate is inserted into a communicating corridor including a supply means and an exhaust means. The substrate is transported while performing the supply and exhaust by sequentially controlling a supply shutoff means, an exhaust shutoff means, and a communicating shutoff means according to the position of a conductance part formed of a gap between the transport means and the communicating corridor.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: October 8, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Kawamura, Yoshifumi Kawamoto, Fumihiko Uchida, Kenichi Mizuishi, Natsuki Yokoyama, Eiichi Murakami, Yoshinori Nakayama, Eiichi Seya
  • Patent number: 5416331
    Abstract: A fine-fabrication method of solid surfaces relates to a new surface fabrication method allows a solid-device surface to be fabricated at an atomic scale so as to produce an ultra-fine device or a device for recording information at an ultra-high density. A probe is installed with a tip thereof facing to the surface of a specimen to undergo fabrication. A voltage for forming an electric field is applied between the probe and the specimen. The electric field is large enough to field-evaporate atoms constituting the specimen or the probe; the electric field field-evaporates atoms constituting the specimen, removing them from the surface of the specimen; and as another alternative, the electric field field-evaporates atoms constituting the probe, depositing them on the surface of the specimen.
    Type: Grant
    Filed: September 11, 1992
    Date of Patent: May 16, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Ichikawa, Shigeyuki Hosoki, Fumihiko Uchida, Shigeo Kato, Yoshihisa Fujisaki, Sumiko Fujisaki, Atsushi Kikugawa, Ryo Imura, Hajime Aoi, Kiyokazu Nakagawa, Eiichi Murakami
  • Patent number: 5411430
    Abstract: The present invention provides a hybrid lens having an axially asymmetrical non-spherical shape, good mass productivity, and excellent shape precision surface precision as well as environment resistant property, and a method for fabricating same, as well as a method and a device for a laser printer using that hybrid lens. In particular, there are disclosed a method, by which, when an axially asymmetrical non-spherical convex lens is formed by the replica method, the shape thereof is transcribed with a high precision, as well as a method and a device for fabricating an axially asymmetrical non-spherical concave lens (female die) serving as an original for the transcription. In a device for fabricating a female die by direct grinding, the positions of a rotation axis of an object to be worked and a rotation axis of a grinding wheel are controlled and it has further a function of correcting mounting errors, when the object to be worked and the grinding wheel are mounted.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: May 2, 1995
    Assignees: Hitachi Ltd., Hitachi Koki Co., Ltd.
    Inventors: Takashi Nishimura, Akira Arimoto, Yoshinori Miyamura, Yumiko Anzai, Yoshimasa Kondo, Fumihiko Uchida, Shigeo Moriyama
  • Patent number: 4739161
    Abstract: A fine displacement transducer, wherein either end of a first and a second optical fibers which are mutually adjacent are respectively provided in alignment with each other opposed to the reflection surface and the illuminating light is made incident from the one end of the first optical fiber and the light irradiated from the other end of the first optical fiber is made to illuminate its reflection surface, while the reflected light therefrom is received by the second optical fiber, so that the amount of displacement of the reflection surface relative to both end surfaces of the second optical fiber can be detected from the variation of intensity of the received light, and a measuring system wherein the reflected light from the reflection surface is received by either of the second or a separately provided third optical fiber to detect the intensity of received light for converting it into the electric signal.
    Type: Grant
    Filed: June 5, 1986
    Date of Patent: April 19, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Moriyama, Fumihiko Uchida