Abstract: To provide an analog mixer circuit operating with low power consumption and without needing any BEF for isolating two input signals, an LO signal and an IF signal are supplied to bases of a first transistor (Q1) and a second transistor (Q2) serially connected. A signal of a node (17) where the emitter of the first transistor (Q1) and the collector of the second transistor (Q2) is amplified nonlinearly by a third transistor (Q3) to be output to an output terminal (11), wherefrom an RF signal is extracted by a HPF (18).

Abstract: A mixer circuit includes a first transistor and a second transistor of different conduction types which are connected and the emitter of the first transistor is connected to the collector of the second transistor, and the collector of the first transistor is connected to the emitter of the second transistor, a third transistor, whose collector is connected to the emitter of the first transistor, a power supply terminal connected to the collector of the first transistor, a radio frequency (RF) terminal connected to the collector of the first transistor, a local signal (LO) terminal connected to the base of the first transistor, an intermediate frequency (IF) terminal connected to the base of the second transistor, and a ground terminal connected to the emitter of the third transistor.

Abstract: A double balanced mixer circuit of reduced power consumption includes two single balanced mixer circuits each of which has a pair of first transistors. Output side terminals of the first transistors are cross-coupled between the two pairs, and first differential signals are supplied to control terminals of the first transistors. Connected in series to each pair of first transistors is a second transistor of a pair of second transistors. The double balanced mixer circuit also includes a differential amplifier circuit including a pair of third transistors, with fourth transistors connected to the pair of third transistors. The fourth transistors function as constant current sources for the pair of third transistors. Second differential signals are supplied to control terminals of the third transistors and differential output terminals of the third transistors are directly coupled to control terminals of the pair of second transistors.

Abstract: A modified non-threshold logic (MNTL) circuit includes an MNTL basic gate circuit and an emitter follower circuit. In the emitter follower circuit, a base of a pull down transistor of the emitter follower circuit which composes a push pull circuitry structure is biased by a clamping transistor and a high resistance resistor, and connected to either an OR output or an input voltage terminal of the MNTL basic gate circuit. In this structure, the pull down transistor becomes ON state with a high impulse response when the OR output or the input voltage terminal becomes high level, so that a propagation delay time of an output signal of the emitter follower circuit is shortened significantly.