Abstract: The number of failure bits is counted with respect to each row and each column in a fail bit map (9), to find respective average numbers of failure bits with respect to rows and columns. One-half of the average number of failure bits of rows is defined as a threshold value of rows, and one-half of the average number of failure bits of columns is defined as a threshold value of columns. Thereafter, on the basis of the respective threshold values of rows and columns, the number of failure bits is converted to digital form with respect to each row and each column. The respective average values of the digitized numbers of failure bits with respect to rows and columns are calculated, which are respectively referred to as average values of rows and columns. It is determined that a semiconductor device contains a block failure in a row direction, a block failure in a column direction, or a random block failure.

Abstract: A failure analysis method is provided that allows high-precision failure mode classification. Based on the result of a predetermined test using an LSI tester (2), an original FBM (27a) is generated. The FBM (27a) is compressed with 8×8 bits per pixel to generate an FBM (27b). Based on the FBM (27b), an area where a failure bit exists in the FBM (27a) is determined. Then, by compressing a portion of the FBM (27a) which corresponds to the above area with 2×2 bits per pixel, FBMs (27c, 27d) are generated. Based on the FBMs (27c, 27d), failure bits are determined.

Abstract: A failure analysis method is provided that allows high-precision failure mode classification. Based on the result of a predetermined test using an LSI tester (2), an original FBM (27a) is generated. The FBM (27a) is compressed with 8×8 bits per pixel to generate an FBM (27b). Based on the FBM (27b), an area where a failure bit exists in the FBM (27a) is determined. Then, by compressing a portion of the FBM (27a) which corresponds to the above area with 2×2 bits per pixel, FBMs (27c, 27d) are generated. Based on the FBMs (27c, 27d), failure bits are determined.

Abstract: A semiconductor device inspecting method is provided which can detect electric faults in an in-line inspection. The positive electrode of a variable DC power supply (2) is connected to the back or a peripheral portion of a semiconductor substrate (4) and the negative electrode of the variable DC power supply (2) is connected to a conductive cantilever (3). A scan is performed with a given forward bias voltage (e.g. 1.0 V) applied between the cantilever (3) and the semiconductor substrate (4) and with the cantilever (3) in contact with a target contact plug (9). The current flowing through the cantilever (3) is then monitored with an ammeter (1) to obtain a current characteristic of each contact plug, making it possible to detect conduction faults which cannot be detected by simply observing the configuration.

Abstract: An insulating film provided on an underlying layer (1) is selectively removed, thereby forming an insulating columnar body (4) standing on the underlying layer (1). A conductive film (7) is provided to cover the columnar body (4). Next, an interlayer insulating film (9) is provided to bury the columnar body (4) and the conductive film (7). The upper surface of the interlayer insulating film (9) is polished and planarized to the extent that the conductive film (7) is exposed. Thereafter an upper interconnect line (10) is provided. A lower interconnect line (8) and the upper interconnect line (10) are thereby connected through the conductive film (7).

Abstract: Provided are a failure analysis method with which it is able to prevent incorrect recognition of fail shapes and to recognize and classify fail shapes at high accuracy, and a recording medium for recording its program, as well as a method of deriving compression thresholds used in the failure analysis method, and a recording medium for recording its program. Specifically, a recognition rule is read (ST1), and a plurality of compressed FBMs, i.e., fail bit maps, are prepared (ST2). After selecting an inferior recognition object (ST3), a predetermined region is selected based on the setting of a fail size (ST4), and the fail rate in the predetermined region is calculated (ST5). Subsequently, under the fail rate condition and the condition as to whether an inferior recognition object is adjacent or not, the inferior recognition object is estimated (ST6), and the fail rates of the remaining compressed FBMs are calculated and normalized (ST7).

Abstract: An EWS for data analysis automatically performs automatic fatal failure extract processing on the basis of FBM information accumulated in a computer for a tester. In the automatic fatal failure extract processing, X-line repair judgment processing and Y-line repair judgment processing are continuously performed so that the X-line repair processing is performed in consideration of failures in a Y-line direction, and the Y-line repair judgment processing is performed in consideration of failures in an X-line direction. Further, the failures in the Y-line and X-line directions are taken into consideration from maximum ability decided by Y-line substitutability and X-line substitutability to zero. Thus provided is a failure analysis system capable of automatically investigating the cause for fatal failures.

Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of foreign material, a defect or the like at the surface of a semiconductor wafer by a defect inspecting apparatus is stored. Also stored is data of physical coordinates obtained based on fail bit data from a tester. Data indicating an additional failure region is produced by an additional failure region estimating apparatus based on the fail bit data, and is stored. Collation produces data of corrected physical position coordinates by adding the stored data of limitation by failure mode to the stored data of physical position coordinates, and collates the data of corrected physical position coordinates with stored data of defect position coordinates. Accordingly, accuracy in collation is improved, and failure can be analyzed even if caused not by a defect located at an address of the failure obtained by the fail bit data but by a defect relating to the defect located at the address of a failure.

Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of a foreign material, a defect and the like at a surface of a semiconductor wafer by a defect inspecting apparatus is stored in storage means. Data of physical position coordinates obtained based on fail bit data from a tester is stored in storage means. Data indicating an additional failure region is produced by additional failure region estimating means based on the fail bit data, and is stored in storage means. Collating means produces data of corrected physical position coordinates by adding the data of limitation by failure mode stored in storage means to the data of physical position coordinates stored in storage means, and collates the data of corrected physical position coordinates with data of defect position coordinates stored in storage means.