Abstract: A vehicle ground fault detection apparatus (1) detects a ground fault of a high-voltage system electrically insulated from a vehicle body connected to a low-voltage system and includes a transformer (2) blocking a DC component between the low- and high-voltage systems, an oscillation circuit (3), in the low-voltage system, connected to a primary coil (21) of the transformer (2), and a voltage dividing resistor (4), in the high-voltage system, connected to a secondary coil (22) of the transformer (2). The vehicle ground fault detection apparatus (1) measures a positive peak of voltage generated in the voltage dividing resistor (4) by voltage induced in the secondary coil (22) through AC voltage generated by the oscillation circuit (3) and detects the ground fault using the peak voltage. The insulation of the coupling portion between the ground fault detection circuit and the high-voltage system circuit does not suffer breakdown during temporary AC noise.

Abstract: A vehicle ground fault detection apparatus (1) detects a ground fault of a high-voltage system electrically insulated from a vehicle body connected to a low-voltage system and includes a transformer (2) blocking a DC component between the low- and high-voltage systems, an oscillation circuit (3), in the low-voltage system, connected to a primary coil (21) of the transformer (2), and a voltage dividing resistor (4), in the high-voltage system, connected to a secondary coil (22) of the transformer (2). The vehicle ground fault detection apparatus (1) measures a positive peak of voltage generated in the voltage dividing resistor (4) by voltage induced in the secondary coil (22) through AC voltage generated by the oscillation circuit (3) and detects the ground fault using the peak voltage. The insulation of the coupling portion between the ground fault detection circuit and the high-voltage system circuit does not suffer breakdown during temporary AC noise.

Abstract: A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.

Abstract: A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.