Patents by Inventor Fumika AKASAWA
Fumika AKASAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11777502Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.Type: GrantFiled: March 12, 2020Date of Patent: October 3, 2023Inventors: Hiroki Inoue, Munehiro Kozuma, Takeshi Aoki, Shuji Fukai, Fumika Akasawa, Sho Nagao
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Publication number: 20220366958Abstract: Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.Type: ApplicationFiled: June 9, 2020Publication date: November 17, 2022Inventors: Fumika AKASAWA, Munehiro KOZUMA
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Publication number: 20220173737Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.Type: ApplicationFiled: March 12, 2020Publication date: June 2, 2022Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroki INOUE, Munehiro KOZUMA, Takeshi AOKI, Shuji FUKAI, Fumika AKASAWA, Sho NAGAO
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Patent number: 11276711Abstract: A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.Type: GrantFiled: November 22, 2017Date of Patent: March 15, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroki Inoue, Fumika Akasawa
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Publication number: 20220045683Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.Type: ApplicationFiled: December 10, 2019Publication date: February 10, 2022Inventors: Hiroki INOUE, Munehiro KOZUMA, Takeshi AOKI, Shuji FUKAI, Fumika AKASAWA, Shintaro HARADA, Sho NAGAO
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Patent number: 10964700Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.Type: GrantFiled: May 28, 2020Date of Patent: March 30, 2021Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
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Publication number: 20200295006Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumika Akasawa, Hiroki INOUE, Takashi NAKAGAWA, Yoshiyuki KUROKAWA
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Patent number: 10672771Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.Type: GrantFiled: October 30, 2018Date of Patent: June 2, 2020Assignee: Semiconductor Energy Labortory Co., Ltd.Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
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Patent number: 10552258Abstract: A semiconductor device that is less likely to be affected by a soft error is provided. The semiconductor device includes a first memory, a second memory, a processor that can be connected to the first memory and the second memory, and a selector for selectively connecting one of the first memory and the second memory to the processor. The probability of occurrence of a soft error of the first memory is higher than that of the second memory. When an error derived from a soft error is detected in the first memory, the selector connects the second memory to the processor. The semiconductor device can stably operate even when moved from an environment where a soft error is less likely to occur to an environment where a soft error is likely to occur.Type: GrantFiled: September 5, 2017Date of Patent: February 4, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumika Akasawa, Seiichi Yoneda
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Patent number: 10545526Abstract: A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.Type: GrantFiled: June 16, 2016Date of Patent: January 28, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroki Inoue, Yoshiyuki Kurokawa, Takashi Nakagawa, Fumika Akasawa
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Publication number: 20190074278Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.Type: ApplicationFiled: October 30, 2018Publication date: March 7, 2019Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
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Patent number: 10128249Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.Type: GrantFiled: December 27, 2016Date of Patent: November 13, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
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Publication number: 20180151593Abstract: A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.Type: ApplicationFiled: November 22, 2017Publication date: May 31, 2018Inventors: Hiroki INOUE, Fumika AKASAWA
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Publication number: 20180081756Abstract: A semiconductor device that is less likely to be affected by a soft error is provided. The semiconductor device includes a first memory, a second memory, a processor that can be connected to the first memory and the second memory, and a selector for selectively connecting one of the first memory and the second memory to the processor. The probability of occurrence of a soft error of the first memory is higher than that of the second memory. When an error derived from a soft error is detected in the first memory, the selector connects the second memory to the processor. The semiconductor device can stably operate even when moved from an environment where a soft error is less likely to occur to an environment where a soft error is likely to occur.Type: ApplicationFiled: September 5, 2017Publication date: March 22, 2018Inventors: Fumika AKASAWA, Seiichi YONEDA
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Patent number: 9870827Abstract: A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.Type: GrantFiled: November 22, 2016Date of Patent: January 16, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Nakagawa, Hiroki Inoue, Fumika Akasawa, Yoshiyuki Kurokawa
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Publication number: 20170186751Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.Type: ApplicationFiled: December 27, 2016Publication date: June 29, 2017Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumika Akasawa, Hiroki INOUE, Takashi NAKAGAWA, Yoshiyuki KUROKAWA
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Publication number: 20170154678Abstract: A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.Type: ApplicationFiled: November 22, 2016Publication date: June 1, 2017Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi NAKAGAWA, Hiroki INOUE, Fumika AKASAWA, Yoshiyuki KUROKAWA
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Publication number: 20160379564Abstract: A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.Type: ApplicationFiled: June 16, 2016Publication date: December 29, 2016Inventors: Hiroki INOUE, Yoshiyuki KUROKAWA, Takashi NAKAGAWA, Fumika AKASAWA