Patents by Inventor Fumiki Aisou

Fumiki Aisou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230413565
    Abstract: A semiconductor device includes a stacked body, a semiconductor layer, a first insulating film, a first charge storage film, a second charge storage film, and a second insulating film. The stacked body includes an electrode layer and an insulating layer alternately stacked in a first direction. The semiconductor layer is disposed in the stacked body in the first direction. The first insulating film is disposed between the stacked body and the semiconductor layer. The first charge storage film is disposed between the stacked body and the first insulating film. The second charge storage film protrudes from the first charge storage film toward the electrode layer in a second direction crossing the first direction. The sum of thicknesses of the first charge storage film and the second charge storage film in the second direction is greater than a thickness of the first charge storage film in the second direction. The second insulating film is disposed between the electrode layer and the second charge storage film.
    Type: Application
    Filed: March 3, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Tatsunori ISOGAI, Fumiki AISOU, Masaki NOGUCHI
  • Publication number: 20010044182
    Abstract: In a semiconductor device, a polycrystalline silicon layer is formed on a semiconductor substrate, and an HSG polycrystalline silicon layer is formed on the polycrystalline silicon layer. The HSG polycrystalline silicon is converted from an amorphous silicon layer.
    Type: Application
    Filed: August 24, 1998
    Publication date: November 22, 2001
    Inventors: TAKASHI SAKOH, FUMIKI AISOU
  • Patent number: 6074925
    Abstract: The method for fabricating a semiconductor device includes steps of forming a layered structure by sequentially depositing a silicon film containing an impurity, a metal silicide film, and an amorphous silicon film containing an impurity, forming an electrode or an interconnect in a three-layer structure by selectively etching the amorphous silicon film, the metal silicide film and the silicon film in this order, and diffusing the impurity in the amorphous silicon film into the metal silicide film by a thermal process. Thus, the impurity is supplied from the amorphous silicon film to the metal silicide film so that the ion-implantation as required in the prior art is not necessary.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventor: Fumiki Aisou
  • Patent number: 5926709
    Abstract: A node contact hole is formed in an inter-level insulating layer through an anisotropic etching using an inner conductive side wall formed in a primary opening as an etching mask, and an outer conductive side wall concurrently formed from a doped polysilicon together with a conductive plug in the node contact hole increases the surface area of a storage node electrode of a stacked storage capacitor.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: July 20, 1999
    Assignee: NEC Corporation
    Inventors: Fumiki Aisou, Toshiyuki Hirota
  • Patent number: 5885889
    Abstract: An intentionally undoped amorphous silicon layer, a phosphorous doped amorphous silicon layer and a tungsten silicide layer are successively laminated on a gate oxide layer, and are patterned into a gate electrode of a field effect transistor; while a phosphosilicate glass layer over the gate electrode is being reflowed, the amorphous silicon layers are crystallized to a polysilicon layer, and phosphorous is less segregated at the boundary between the gate oxide layer and the polysilicon layer during the heat treatment.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: March 23, 1999
    Assignee: NEC Corporation
    Inventor: Fumiki Aisou
  • Patent number: 5850288
    Abstract: In a system for detecting a degree of unevenness of a surface of a semiconductor device, the surface is irradiated with light having a wavelength of approximately 240 nm to 500 nm. The degree of unevenness of the surface is determined in accordance with an intensity of reflected light from the surface.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: December 15, 1998
    Assignee: NEC Corporation
    Inventors: Ichirou Honma, Fumiki Aisou
  • Patent number: 5796484
    Abstract: In a system for detecting a degree of unevenness of a surface of a semiconductor device, the surface is irradiated with light having a wavelength of approximately 240 nm to 500 nm. The degree of unevenness of the surface is determined in accordance with an intensity of reflected light from the surface.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: August 18, 1998
    Assignee: NEC Corporation
    Inventors: Ichirou Honma, Fumiki Aisou
  • Patent number: 5677242
    Abstract: A first opening formed in a photo-resist layer is topographically covered with a spacer layer of silicon oxide so as to define a second opening narrower than the first opening, and the spacer layer and a target layer of silicon oxide therebeneath are anisotropically etched so as to form a contact hole narrower than the first opening in the target layer.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: October 14, 1997
    Assignee: NEC Corporation
    Inventor: Fumiki Aisou
  • Patent number: 5525540
    Abstract: In a method for manufacturing a silicon layer, a silicon layer is grown simultaneously with doping impurities into the silicon layer. Then, an impurity diffusion preventing layer is grown by interrupting this silicon layer growing step at least one time.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: June 11, 1996
    Assignee: NEC Corporation
    Inventors: Masanobu Zenke, Fumiki Aisou