Abstract: To provide a technique of increasing a radius of curvature of (0001) plane, and narrowing an off-angle distribution, there is provided a nitride semiconductor substrate containing a group III nitride semiconductor crystal and having a main surface in which a nearest low index crystal plane is (0001) plane, wherein (0001) plane in one of a direction along <1-100> axis and a direction along <11-20> axis orthogonal to the <1-100> axis, is curved in a concave spherical shape with respect to the main surface, and a radius of curvature of the (0001) plane in one of the direction along the <1-100> axis and the direction along the <11-20> axis orthogonal to the <1-100> axis is different from a radius of curvature of at least a part of the (0001) plane in the other direction.

Abstract: There is provided a laminated substrate having a piezoelectric film, including: a substrate; a first electrode film provided on the substrate; and a piezoelectric film provided on the first electrode film, wherein an oxide film containing an oxide represented by a composition formula of RuOx or IrOx, is provided on the piezoelectric film.

Abstract: There is provided a method for measuring a film thickness of a thin film in a nitride semiconductor laminate having the thin film homoepitaxially grown on a substrate comprising group-III nitride semiconductor crystal, wherein the film thickness of the thin film is measured using the substrate having a carrier concentration and an infrared absorption coefficient which are interdependent, and using Fourier Transform Infrared Spectroscopy method or Infrared Spectroscopic Ellipsometry method.

Abstract: A semiconductor device is included a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor, a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of 1×1020 cm?3 or more, a first electrode disposed in contact with the first semiconductor layer, and a second electrode disposed in contact with the second semiconductor layer, and the semiconductor device functions as a pn-junction diode.

Abstract: Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0?x?1, 0?y?1, 0?x+y?1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm?1 or more and 4.6 cm?1 or less under a temperature condition of normal temperature.

Abstract: There is provided a nitride crystal substrate comprising group-III nitride crystal and containing n-type impurities, wherein an absorption coefficient ? is approximately expressed by equation (1) in a wavelength range of at least 1 ?m or more and 3.3 ?m or less: ?=n K?a (1) (wherein, ?(?m) is a wavelength, ?(cm?1) is absorption coefficient of the nitride crystal substrate at 27° C., n (cm?3) is a free electron concentration in the nitride crystal substrate, and K and a are constants, satisfying 1.5×10?19?K?6.0×10?19, a=3).

Abstract: A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure an

Abstract: There is provided a new technology for anodic oxidation etching performed to GaN material having arithmetic mean line roughness Ra of 15 nm or less at a measurement length of 100 ?m on a bottom surface of a recess when anodic oxidation etching is performed at an etching voltage of 1 V while irradiating the GaN material with UV light to form the recess of 2 ?m in depth.

Abstract: There is provided a laminated substrate having a piezoelectric film, including: a substrate; and a piezoelectric film provided on the substrate interposing a base film, wherein the piezoelectric film has an alkali niobium oxide based perovskite structure represented by a composition formula of (K1-xNax)NbO3 (0<x<1) and preferentially oriented in (001) plane direction, and a sound speed of the piezoelectric film is 5100 m/s or more.

Abstract: This method for manufacturing a lead-free niobate-system ferroelectric thin film device includes: a lower electrode film formation step of forming a lower electrode film on a substrate; a ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask pattern formation step of forming an etch mask in a desired pattern on the niobate-system ferroelectric thin film; and a ferroelectric thin film etching step of shaping the niobate-system ferroelectric thin film into a desired fine pattern by wet etching using an etchant comprising: a predetermined chelating agent including at least one selected from EDTMP, NTMP, CyDTA, HEDP, GBMP, DTPMP, and citric acid; an aqueous alkaline solution containing an aqueous ammonia solution; and an aqueous hydrogen peroxide solution.

Abstract: A manufacturing method of a group-III nitride laminate includes: preparing a group-III nitride laminate having a group-III nitride substrate and a group-III nitride epitaxial layer formed above a main surface of the group-III nitride substrate; and conducting photoluminescence mapping measurement at a plurality of measurement positions on the group-III nitride epitaxial layer, where a magnitude of an off-angle is different, the off-angle being formed by a normal direction of the main surface of the group-III nitride substrate and c-axis direction, to obtain a relative yellow intensity which is a rate of a yellow emission intensity to a band edge emission intensity, and obtain a correspondence relationship between a magnitude of the off-angle and the relative yellow intensity.

Abstract: There is provided a nitride crystal substrate having a main surface and formed of group-III nitride crystal, wherein NIR/NElec, satisfies formula (1) below, which is a ratio of a carrier concentration NIR at a center of the main surface relative to a carrier concentration NElec: 0.5?NIR/NElec?1.5 . . . (1) where NIR is the carrier concentration on the main surface side of the nitride crystal substrate obtained based on a reflectance of the main surface measured by a reflection type Fourier transform infrared spectroscopy, and NElec is the carrier concentration in the nitride crystal substrate obtained based on a specific resistance of the nitride crystal substrate and a mobility of the nitride crystal substrate measured by an eddy current method.

Abstract: There is provided a piezoelectric laminate, including: a substrate; and a piezoelectric film formed on the substrate, wherein the piezoelectric film is a film containing an alkali niobium oxide of a perovskite structure represented by a composition formula of (K1-xNax)NbO3 (0<x<1), and having Young's modulus of less than 100 GPa.

Abstract: A nitride semiconductor substrate is manufactured by a method which includes growing nitride semiconductor crystal along a c-axis direction on a +C-plane of a seed crystal substrate formed of nitride semiconductor crystal to form an n?-type first nitride semiconductor layer; growing the nitride semiconductor crystal along the c-axis direction on the +C-plane of the first nitride semiconductor layer to form a second nitride semiconductor layer; and removing the seed crystal substrate and exposing a ?C-plane of the first nitride semiconductor layer to obtain as a semiconductor substrate a laminate of the first nitride semiconductor layer and the second nitride semiconductor layer, with the ?C plane as a main surface.

Abstract: There is provided a nitride crystal substrate constituted by group-III nitride crystal, containing n-type impurities, with an absorption coefficient ? being approximately expressed by equation (1) by a least squares method in a wavelength range of at least 1 ?m or more and 3.3 ?m or less. ?=NeK?a??(1) (where 1.5×10?19?K?6.0×10?19, a=3), here, a wavelength is ? (?m), an absorption coefficient of the nitride crystal substrate at 27° C. is ? (cm?1), a carrier concentration in the nitride crystal substrate is Ne (cm?3), and K and a are constants, wherein an error of an actually measured absorption coefficient with respect to the absorption coefficient ? obtained from equation (1) at a wavelength of 2 ?m is within ±0.1?, and in a reflection spectrum measured by irradiating the nitride crystal substrate with infrared light, there is no peak with a peak top within a wavenumber range of 1,200 cm?1 or more and 1,500 cm?1 or less.

Abstract: There is provided a ferroelectric thin-film laminated substrate, including a substrate, and further including a lower electrode layer, a ferroelectric thin-film layer, an upper electrode intermediate layer, and an upper electrode layer being sequentially stacked on the substrate, in which: the lower electrode layer is made of platinum or a platinum alloy; the ferroelectric thin-film layer is made of a sodium potassium niobate (typical chemical formula of (K1-xNax)NbO3, 0.4?x?0.7); the upper electrode layer is made of aluminum or an aluminum alloy; the upper electrode intermediate layer is made of a metal that has less oxidizability than titanium and can generate an intermetallic compound with Aluminum; and a part of the upper electrode intermediate layer and a part of the upper electrode layer are alloyed.

Abstract: There is provided a semiconductor device, including: a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode electrically connec

Abstract: There is provided a gallium nitride laminated substrate including: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.

Abstract: There is provided a piezoelectric laminate, including: a substrate; and a piezoelectric film formed on the substrate, wherein the piezoelectric film contains an alkali niobium oxide represented by a composition formula of (K1?xNax)NbO3 (0<x<1), having a perovskite structure, and contains a metallic element selected from a group consisting of Cu and Mn at a concentration of more than 0.6 at % and 2.0 at % or less.

Abstract: There is provided a new technology for anodic oxidation etching performed to GaN material having arithmetic mean line roughness Ra of 15 nm or less at a measurement length of 100 ?m on a bottom surface of a recess when anodic oxidation etching is performed at an etching voltage of 1 V while irradiating the GaN material with UV light to form the recess of 2 ?m in depth.