Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first fin structure and a second fin structure over a substrate, a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, a dielectric feature disposed over the first source/drain feature, and a contact structure formed over the first source/drain feature and the second source/drain feature. The contact structure is electrically coupled to the second source/drain feature and is separated from the first source/drain feature by the dielectric feature.

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

Abstract: A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source/drain feature connected to the channel member and adjacent to the gate structure, a source/drain contact disposed below and connected to the source/drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source/drain contact. The first dielectric layer includes a low-k dielectric material.

Abstract: A semiconductor device includes a fin disposed on a substrate, a first dielectric layer disposed over the fin, a first contact extending through the first dielectric layer to a first depth and electrically coupled to the fin, and a second contact extending through the first dielectric layer to a second depth different than the first depth. The first contact has a first bottom portion having a first cross-sectional shape profile. The second contact being electrically isolated from the fin and having a second bottom portion having a second cross-sectional shape profile different than the first cross-sectional shape profile. The semiconductor device also includes a first protective layer disposed along the first contact without being disposed on at least a portion of the first bottom portion of the first contact, and a second protective layer disposed along the second contact including along the second bottom portion of the second contact.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

Abstract: A semiconductor device includes a first transistor in a first region of a first conductivity type and a second transistor in a second region of a second conductivity type opposite to the first conductivity type. The first transistor includes a first gate stack, a first epitaxial feature in a source/drain (S/D) region of the first region, and a first metal silicide layer over the first epitaxial feature. The second transistor includes a second gate stack, a second epitaxial feature in an S/D region of the second region, a dopant-containing implant layer over the second epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant. A lowest point of a top surface of the first epitaxial feature is below a lowest point of a top surface of the second epitaxial feature.

Abstract: A semiconductor device includes a fin-shape structure protruding from a substrate, a gate stack disposed above the fin-shape structure, an epitaxial feature disposed above the fin-shape structure, and a gate spacer disposed on a sidewall of the gate stack. The gate spacer includes an air gap. The air gap exposes a portion of the epitaxial feature.

Abstract: A silicon compound, a preparation method thereof, and a lithium battery are provided. The silicon compound is represented by the following Chemical formula 1: (R1)m—Si—(L—A)n ??[Chemical formula 1] In Chemical formula 1, each substituent is defined the same as in the specification.

Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

Abstract: A controller for managing a battery pack includes: a detection terminal, for transmitting an enable signal when values of battery parameters for the battery pack satisfy a sleep condition, where the enable signal enables the detection circuit to detect whether the battery pack is connected to a load and whether the battery pack is connected to the charger; and a receiving terminal, for receiving a detection result transmitted by the detection circuit. The detection result indicates whether the battery pack is connected to at least one of the load and charger. The controller controls the battery pack to enter a sleep mode of the sleep modes based on the detection result. The controller also includes a control terminal, for transmitting a control signal to control an on/off state of a charging switch and/or a discharging switch. The control signal is generated by the controller based on the detection result.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.