Patents by Inventor Fuminobu Ono
Fuminobu Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160349596Abstract: An actuator for camera which drives a lens unit of a camera includes an outer frame, an inner frame which houses and holds the lens unit and is positioned inside the outer frame, a plurality of first supporting members which are provided between the outer frame and the inner frame and support the inner frame with respect to the outer frame so that the inner frame is displaceable in an optical axis direction of the lens unit, a first driving coil which is attached on an outer circumferential surface of the inner frame and drives the inner frame in the optical axis direction, and permanent magnets which are attached to the outer frame in a manner to be opposed to the first driving coil. The first supporting members are made of elastomer and have a shape of which a center line is a straight line which connects mutually opposed portions of the outer frame and the inner frame. An actuator for camera which is superior in productivity, reliability, and durability can be obtained.Type: ApplicationFiled: April 8, 2016Publication date: December 1, 2016Applicant: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITEDInventors: Takahiro YAMAJI, Akihiro MATSUNAGA, Hiroshi AKIMOTO, Kazuaki IBARAKI, Fuminobu ONO, Jun SHINDOU
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Patent number: 6639452Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (0V) even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.Type: GrantFiled: December 16, 2002Date of Patent: October 28, 2003Assignee: NEC Compound Semiconductor Devices, Ltd.Inventors: Fuminobu Ono, Yoshikazu Nishimura
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Patent number: 6639453Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately 0V even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a diode with a specific forward voltage drop generated by a current flowing through the diode itself. The absolute value of the output bias voltage is decreased by the value of the forward voltage drop of the diode compared with the case where the diode is not provided. The diode is provided between the source/emitter of the third transistor and the drain/collector of the fourth transistor, or between the connection point of the third and fourth transistors and the output terminal, or the gates/bases of the first and third transistors.Type: GrantFiled: February 26, 2001Date of Patent: October 28, 2003Assignee: NEC Compound Semiconductor Devices, Ltd.Inventors: Yoshikazu Nishimura, Fuminobu Ono
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Publication number: 20030085756Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (0V) even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.Type: ApplicationFiled: December 16, 2002Publication date: May 8, 2003Inventors: Fuminobu Ono, Yoshikazu Nishimura
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Patent number: 6515538Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (OV) even if a reference voltage applied to generate a reference current does not reach OV. This circuit comprises cascode-connected first and second transistors cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.Type: GrantFiled: April 18, 2001Date of Patent: February 4, 2003Assignee: NEC Compound Semiconductor Devices, Ltd.Inventors: Fuminobu Ono, Yoshikazu Nishimura
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Publication number: 20010033194Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (0 V) even if a reference voltage applied to generate a reference current does not reach 0 V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.Type: ApplicationFiled: April 18, 2001Publication date: October 25, 2001Applicant: NEC CorporationInventors: Fuminobu Ono, Yoshikazu Nishimura
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Publication number: 20010019287Abstract: An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately 0V even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a diode with a specific forward voltage drop generated by a current flowing through the diode itself. The absolute value of the output bias voltage is decreased by the value of the forward voltage drop of the diode compared with the case where the diode is not provided. The diode is provided between the source/emitter of the third transistor and the drain/collector of the fourth transistor, or between the connection point of the third and fourth transistors and the output terminal, or the gates/bases of the first and third transistors.Type: ApplicationFiled: February 26, 2001Publication date: September 6, 2001Applicant: NEC CorporationInventors: Yoshikazu Nishimura, Fuminobu Ono
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Patent number: 6078020Abstract: In semiconductor device manufacturing apparatus and method, in a joining process of a semiconductor pellet (2) and a package (1), the semiconductor pellet (2) is kept to a temperature equilibrium state under an actual use temperature condition while a low melting-point soldering member (3) is interposed between the semiconductor pellet (2) and the package (1), and the electrode pads (9) on the upper surface of the semiconductor pellet (2) and the electrode terminals (8) of the collet (5), which is electrically connected to the output terminal of a high voltage electric pulse source (4), are fitted and electrically connected to each other. Subsequently, a high voltage electric pulse is produced in the high voltage electric pulse source (4) and applied to the electrode pads (9) to melt the low melting-point soldering member (3), causing joining of the package (1) and the semiconductor pellet (2).Type: GrantFiled: November 13, 1997Date of Patent: June 20, 2000Assignee: NEC CorporationInventor: Fuminobu Ono
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Patent number: 4733478Abstract: This disclosure relates to a process for steam dewatering of brown coal, using a plurality of autoclaves, each of which, in cyclic sequence among the autoclaves, repeats a batch process comprised of an atmospheric pressure stage to unload the coal dewatered and to load the coal to be dewatered, a heating stage to heat and dewater the loaded coal and a depressurizing stage to lower the interior pressure for the unloading of coal, wherein the heating stage comprises first and second steaming steps successive in this order at the final period of this stage to be supplied with fresh steam from an external source, and an initial steaming step under which the autoclave is connected with the other autoclave undergoing the second heating step, thereby intensifying the steam ventilation at the second heating step.Type: GrantFiled: October 6, 1986Date of Patent: March 29, 1988Assignee: Kawasaki Jukogyo Kabushiki KaishaInventors: Takao Kamei, Fuminobu Ono, Keiichi Komai, Takeshi Wakabayashi
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Patent number: 4702745Abstract: A high moisture porous organic solid is dewatered by the steps of (1) heating the high moisture porous organic solid in a fluid medium having an elevated temperature and a high pressure, thereby reducing the moisture of the solid, (2) starting to compress the porous structure of the solid by mechanical means, while maintaining the temperature and the pressure of the surrounding fluid medium the same as in the final stage of step (1), and (3) lowering the pressure of the surrounding fluid medium while maintaining the mechanical compression of the solid, whereby the quality of the porous solid, such as apparent density and calorific values of moist solid per weight as well as per volume are considerably improved.Type: GrantFiled: May 1, 1986Date of Patent: October 27, 1987Assignees: Kawasaki Jukogyo Kabushiki Kaisha, Electric Power Development Co., Ltd.Inventors: Takao Kamei, Fuminobu Ono, Keiichi Komai, Takeshi Wakabayashi, Takayuki Ogawa, Hideaki Ito, Kiyoshi Shirakawa