Abstract: In one embodiment, a semiconductor chip includes a gate electrode extending between a source electrode and a drain electrode. The source electrode and the drain electrode include finger form electrodes that are an engaged arrangement with each other. One or more gate drawing electrodes are connected to portions of the gate electrode, and protrusion electrodes connect the gate drawing electrodes to a gate shunting wiring disposed on a substrate.

Abstract: The invention is directed to realizing a power MOS transistor of high efficiency by enhancing the switching performance of a power MOS transistor having a low on-resistance characteristic more than conventional. A semiconductor chip which includes a gate electrode extending between a source electrode and a drain electrode which include finger form electrodes from one end portion to another end portion of the finger form electrodes, gate drawing electrodes connected to the end portions of the gate electrode through contact holes formed in an interlayer insulation film, a passivation film covering the interlayer insulation film, gate connection electrodes which are portions of the gate drawing electrodes and exposed in openings of the passivation film, and protrusion electrodes formed on the gate connection electrodes, is connected to a low resistance substrate wiring for shunting the gate electrode formed on the front surface of a BGA substrate by the protrusion electrodes.

Abstract: In order to prevent interference of signals in a plurality of outputs from a current mirror circuit, the current mirror circuit comprises a current mirror input transistor Q1 through which a constant current flows and a plurality of current mirror output transistors Q7 and Q8 which have control ends commonly connected to a control end of the current mirror input transistor Q1. The constant current is supplied from the plurality of current mirror output transistors Q7 and Q8 to a plurality of operating circuits. Further, at least one of the plurality of current mirror output transistors Q7 and Q8 is equipped with a low pass filter for removing a high-frequency component contained in a current output from the at least one of the plurality of current mirror output transistors Q7 and Q8.

Abstract: This invention is directed to improve the electrostatic discharge strength and the latch-up strength of the semiconductor integrated circuit. To achieve the certain level of stable quality of the semiconductor integrated circuit by eliminating the variety in the electrostatic discharge strength and the latch-up strength is also aimed. The first NPN type bipolar transistor 3 and the second NPN type bipolar transistor 4 in the electrostatic discharge protection cell EC 1 are surrounded by the isolation region 6 made of the P+ type semiconductor layer and electronically isolated from other elements. The width WB1 of the isolating region 6 is larger than the width WB2 of the isolation region 7 that separates the elements comprising the internal circuit 50 from each other. This configuration can efficiently improve the electrostatic discharge strength and the latch-up strength.

Abstract: A current mirror circuit includes a first transistor, a plurality of second transistors whose bases are connected to a base of the first transistor, and a compensation transistor having a gate connected to a collector of the first transistor, a source and a back gate connected to the base of the first transistor and the bases of the plurality of second transistors, and a drain connected to a power source. The first transistor and the plurality of second transistors are bipolar transistors. The compensation transistor is a MOS-type transistor. A current corresponding to a current flowing in the first transistor is permitted to flow in the plurality of second transistors.

Abstract: This invention is directed to improve the electrostatic discharge strength and the latch-up strength of the semiconductor integrated circuit. To achieve the certain level of stable quality of the semiconductor integrated circuit by eliminating the variety in the electrostatic discharge strength and the latch-up strength is also aimed. The first NPN type bipolar transistor 3 and the second NPN type bipolar transistor 4 in the electrostatic discharge protection cell EC 1 are surrounded by the isolation region 6 made of the P+ type semiconductor layer and electronically isolated from other elements. The width WB1 of the isolating region 6 is larger than the width WB2 of the isolation region 7 that separates the elements comprising the internal circuit 50 from each other. This configuration can efficiently improve the electrostatic discharge strength and the latch-up strength.

Abstract: An amplifier which amplifies an input signal, wherein an amplified signal which varies with a ground voltage as a center is obtained at an output of the amplifier using a positive power supply and a negative power supply. With this configuration, an amplified signal which varies with the ground voltage as a center can be obtained at the output of the amplifier so that a direct current cutting capacitor is no longer necessary.

Abstract: In order to prevent interference of signals in a plurality of outputs from a current mirror circuit, the current mirror circuit comprises a current mirror input transistor Q1 through which a constant current flows and a plurality of current mirror output transistors Q7 and Q8 which have control ends commonly connected to a control end of the current mirror input transistor Q1. The constant current is supplied from the plurality of current mirror output transistors Q7 and Q8 to a plurality of operating circuits. Further, at least one of the plurality of current mirror output transistors Q7 and Q8 is equipped with a low pass filter for removing a high-frequency component contained in a current output from the at least one of the plurality of current mirror output transistors Q7 and Q8.

Abstract: Adverse effects of switching noise produced by a charge pump circuit on a displayed image are prevented. In a synchronizing separation circuit 18, a synchronizing signal is separated from a video signal. The separated synchronizing signal is subjected to ½ frequency division in a flip-flop 20 to obtain a clock signal having a period which is two times as much as one horizontal period, and this clock signal is utilized to control switching of the charge pump circuit. As a result, a timing at which each switch in the charge pump is changed over can be set in a period close to a horizontal synchronizing signal without a video signal, thereby preventing noise from affecting the video signal.

Abstract: A charge pump circuit which uses a constant current from a constant current source for charging or discharging a capacitor and which obtains an output voltage by shifting a power supply voltage using a charged voltage of the charged capacitor. With this structure, a large current can be limited and generation of noise can be prevented.

Abstract: Adverse effects of switching noise produced by a charge pump circuit on a displayed image are prevented. In a synchronizing separation circuit 18, a synchronizing signal is separated from a video signal. The separated synchronizing signal is subjected to ½ frequency division in a flip-flop 20 to obtain a clock signal having a period which is two times as much as one horizontal period, and this clock signal is utilized to control switching of the charge pump circuit. As a result, a timing at which each switch in the charge pump is changed over can be set in a period close to a horizontal synchronizing signal without a video signal, thereby preventing noise from affecting the video signal.

Abstract: A charge pump circuit which uses a constant current from a constant current source for charging or discharging a capacitor and which obtains an output voltage by shifting a power supply voltage using a charged voltage of the charged capacitor. With this structure, a large current can be limited and generation of noise can be prevented.

Abstract: An amplifier which amplifies an input signal, wherein an amplified signal which varies with a ground voltage as a center is obtained at an output of the amplifier using a positive power supply and a negative power supply. With this configuration, an amplified signal which varies with the ground voltage as a center can be obtained at the output of the amplifier so that a direct current cutting capacitor is no longer necessary.