Patents by Inventor Fuminori Higashi

Fuminori Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9106877
    Abstract: A video signal processing apparatus (and method) includes a section determination unit which detects a non-equidistant section having different intervals between a plurality of sample points set for a range from a minimum signal level to a maximum signal level of a video signal to be inputted, correction level holding unit which holds a signal level of a video signal after correction for each sample point as a correction level, and an interpolation computation unit which obtains a signal level of the video signal after correction corresponding to the signal level of the inputted video signal by executing cubic interpolation computation with reference to the correction level held by the correction level holding unit.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 11, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Fuminori Higashi
  • Patent number: 8363168
    Abstract: A difference sample data holder of a gamma correction device holds as difference sample data a difference between a corrected signal level and a yet-to-be-corrected signal level for each of multiple sample points set at equal intervals between the permissible minimum and maximum levels of an input video signal. A correction execution unit performs cubic interpolation operation using the difference sample data held in the difference sample data holder, and adds the operated result and the signal level of the input video signal to obtain the signal level of the corrected video signal.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: January 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Uchinuno, Fuminori Higashi
  • Publication number: 20120274854
    Abstract: A video signal processing apparatus (and method) includes a section determination unit which detects a non-equidistant section having different intervals between a plurality of sample points set for a range from a minimum signal level to a maximum signal level of a video signal to be inputted, a correction level holding unit which holds a signal level of a video signal after correction for each sample point as a correction level, and an interpolation computation unit which obtains a signal level of the video signal after correction corresponding to the signal level of the inputted video signal by executing cubic interpolation computation with reference to the correction level held by the correction level holding unit
    Type: Application
    Filed: July 10, 2012
    Publication date: November 1, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Fuminori Higashi
  • Patent number: 8248493
    Abstract: A video signal processing apparatus includes a non-equidistant section determination circuit, a sample data register, and an interpolation computation circuit. The non-equidistant section determination circuit detects a non-equidistant section having different intervals between plural sample points set for the dynamic range of a video signal to be inputted. The sample data register holds the signal level (correction level) of a video signal after correction for each sample point. The interpolation computation circuit obtains the signal level of the video signal after correction by executing cubic interpolation computation with reference to the correction level. Here, a first section is defined as a section located on a lower signal level side and having intervals of X (X>0) between sample points, and a second section is defined as a section located on a higher level side and having intervals of Y (Y>0, X?Y) between sample points.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: August 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Fuminori Higashi
  • Patent number: 7933465
    Abstract: When performing arithmetic processing on unprocessed image data with use of a target pixel and reference pixels in its proximity, buffers of a number corresponding to the number of lines required for the arithmetic processing, which are a first buffer and a second buffer, are used as intermediate storage units. Each buffer has a capacity that is smaller than a size of a line of the unprocessed image data and equal to or larger than a size required for the arithmetic processing in a main scanning direction. In each arithmetic processing, a pixel from each line in the unprocessed image data is input one by one to a storage region at the right end of a corresponding buffer, and a pixel is read and output from each position of each buffer that is determined according to a positional relationship between a target pixel and its reference pixel. Each time arithmetic processing is performed in each line, data is shifted one pixel from the right end to the left end in the first buffer and the second buffer.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: April 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Fuminori Higashi
  • Publication number: 20090086102
    Abstract: A difference sample data holder of a gamma correction device holds as difference sample data a difference between a corrected signal level and a yet-to-be-corrected signal level for each of multiple sample points set at equal intervals between the permissible minimum and maximum levels of an input video signal. A correction execution unit performs cubic interpolation operation using the difference sample data held in the difference sample data holder, and adds the operated result and the signal level of the input video signal to obtain the signal level of the corrected video signal.
    Type: Application
    Filed: August 15, 2008
    Publication date: April 2, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Shinji Uchinuno, Fuminori Higashi
  • Publication number: 20090051818
    Abstract: A video signal processing device includes a sample data register to hold a signal level of a video signal after correction at each sample point as a correction level, a coefficient operation circuit to output a first coefficient, a coefficient selection circuit to output a second coefficient, and an interpolation operation unit to calculate a signal level of a video signal after correction corresponding to a signal level of the input video signal by using the correction level held in the sample data register, the first coefficient or the second coefficient and performing the cubic interpolation operation or the linear interpolation operation. The first coefficient is used when a video signal after correction is obtained from the input video signal by a linear interpolation operation. The second coefficient is used when a video signal after correction is obtained from the input video signal by a cubic interpolation operation.
    Type: Application
    Filed: August 18, 2008
    Publication date: February 26, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Takashi FURUKAWA, Fuminori HIGASHI
  • Publication number: 20090027559
    Abstract: A video signal processing apparatus includes a non-equidistant section determination circuit, a sample data register, and an interpolation computation circuit. The non-equidistant section determination circuit detects a non-equidistant section having different intervals between plural sample points set for the dynamic range of a video signal to be inputted. The sample data register holds the signal level (correction level) of a video signal after correction for each sample point. The interpolation computation circuit obtains the signal level of the video signal after correction by executing cubic interpolation computation with reference to the correction level. Here, a first section is defined as a section located on a lower signal level side and having intervals of X (X>0) between sample points, and a second section is defined as a section located on a higher level side and having intervals of Y (Y>0, X?Y) between sample points.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 29, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Fuminori Higashi
  • Publication number: 20080069465
    Abstract: When performing arithmetic processing on unprocessed image data with use of a target pixel and reference pixels in its proximity, buffers of a number corresponding to the number of lines required for the arithmetic processing, which are a first buffer and a second buffer, are used as intermediate storage units. Each buffer has a capacity that is smaller than a size of a line of the unprocessed image data and equal to or larger than a size required for the arithmetic processing in a main scanning direction. In each arithmetic processing, a pixel from each line in the unprocessed image data is input one by one to a storage region at the right end of a corresponding buffer, and a pixel is read and output from each position of each buffer that is determined according to a positional relationship between a target pixel and its reference pixel. Each time arithmetic processing is performed in each line, data is shifted one pixel from the right end to the left end in the first buffer and the second buffer.
    Type: Application
    Filed: September 12, 2007
    Publication date: March 20, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Fuminori Higashi