Abstract: An integrated circuit layout design system and a power source eliminating method to be employed in the same can realize high wiring receiving capability, can achieve speeding up by shortening delay period of signal wiring, significantly eliminate design load, and can prevent lowering of function. The integrated circuit layout designing system performs a layout design of an integrated circuit having a basic power source wiring structure consisted of a power source wiring and a grounding wiring. The integrated circuit layout designing system also eliminates the power source wiring and a power source via other than the basic power source wiring structure for supplying a power to a function block after arranging the function block on the basic power source wiring structure.

Abstract: An electronic device assembly includes a large-scale-integrated circuit (LSI) chip having center and peripheral portions. A circuit and terminals are formed in the center in and peripheral portions, respectively. A carrier substrate is attached to the center portion of the LSI chip. The carrier substrate has center and peripheral portions. Bumps and terminals are provided in the center and peripheral portions of the carrier substrate. Wires connect the terminals of the LSI chip and the carrier substrate. The carrier substrate is mounted on a substrate via the bumps. The thermal expansion coefficient of the carrier substrate is between those of the LSI chip and the substrate.