Patents by Inventor Fuminori Mitsuhashi
Fuminori Mitsuhashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240093379Abstract: To treat a corner of an etched metal machined article by a method other than polishing. A method includes: forming a protective layer 200 on each of a front surface 120 and a back surface 140 of a metal plate 100 while a side surface 160 of the metal plate 100 is exposed; cutting out a precursor 300 of a component to be manufactured from the metal plate 100 on which the protective layer 200 is formed; etching the precursor 300 without removing the protective layer 200; chamfering a corner between the front surface 120 and the side surface 160 and a corner between the back surface 140 and the side surface 160 of the etched precursor 300 by an electrical or chemical treatment; and removing the protective layer 200 from the chamfered precursor 300.Type: ApplicationFiled: October 11, 2020Publication date: March 21, 2024Applicant: UNITED PRECISION TECHNOLOGIES CO., LTD.Inventors: FUMINORI MITSUHASHI, TAKUNORI MATSUBARA
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Patent number: 11884546Abstract: A multilayer body includes a base portion and a graphene film. In an ion mass distribution versus depth of the multilayer body determined by time-of-flight secondary ion mass spectrometry, detection intensities of C6 ions have a maximum value at a depth of greater than 0 nm and 2.5 nm or less from an exposed surface. Detection intensities of C3 ions have a maximum value at a depth of greater than 0 nm and 3.0 nm or less from the exposed surface. Detection intensities of SiC4 ions have a maximum value at a depth of 0.5 nm or greater and 5.0 nm or less from the exposed surface. Detection intensities of SiC ions have a maximum value at a depth of 0.5 nm or greater and 10.0 nm or less from the exposed surface. Detection intensities of Si2 ions have a maximum value at a depth of 0.5 nm or greater and 10.0 nm or less from the exposed surface.Type: GrantFiled: September 20, 2019Date of Patent: January 30, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Fuminori Mitsuhashi, Yasunori Tateno, Masahiro Adachi, Yoshiyuki Yamamoto
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Patent number: 11881394Abstract: A stack includes a base portion consisting of silicon carbide and having a first surface that is a Si face and a carbon atom thin film disposed on the first surface and including a first main surface facing the first surface and a second main surface that is a main surface on an opposite side from the first main surface. The carbon atom thin film consists of carbon atoms. The carbon atom thin film includes at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the Si face and a graphene layer. The second main surface includes a plurality of terraces parallel to the Si face of the silicon carbide forming the base portion and a plurality of steps connecting together the plurality of terraces.Type: GrantFiled: March 26, 2020Date of Patent: January 23, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Fuminori Mitsuhashi, Yasunori Tateno, Masahiro Adachi, Yoshiyuki Yamamoto
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Publication number: 20220231123Abstract: A stack includes a base portion consisting of silicon carbide and having a first surface that is a Si face and a carbon atom thin film disposed on the first surface and including a first main surface facing the first surface and a second main surface that is a main surface on an opposite side from the first main surface. The carbon atom thin film consists of carbon atoms. The carbon atom thin film includes at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the Si face and a graphene layer. The second main surface includes a plurality of terraces parallel to the Si face of the silicon carbide forming the base portion and a plurality of steps connecting together the plurality of terraces.Type: ApplicationFiled: March 26, 2020Publication date: July 21, 2022Applicant: Sumitomo Electric Industries, Ltd.Inventors: Fuminori MITSUHASHI, Yasunori TATENO, Masahiro ADACHI, Yoshiyuki YAMAMOTO
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Publication number: 20220123156Abstract: A photosensor includes: a support; a thermoelectric conversion material section that is disposed on a first main surface of the support and that includes a plurality of first material layers each having an elongated shape, a plurality of second material layers each having electrical conductivity and an elongated shape, and an insulating film, the first material layers and the second material layers each being configured to convert thermal energy into electrical energy; a heat sink that is disposed on a second main surface of the support and along an outer edge of the support; a light-absorbing film that is disposed in a region surrounded by inner edges of the heat sink as viewed in a thickness direction of the support so as to form temperature differences on the first main surface of the support in longitudinal directions of the first material layers.Type: ApplicationFiled: January 3, 2022Publication date: April 21, 2022Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kotaro HIROSE, Masahiro ADACHI, Yoshiyuki YAMAMOTO, Shunsuke FUJII, Fuminori MITSUHASHI
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Publication number: 20220064005Abstract: A multilayer body includes a base portion and a graphene film. In an ion mass distribution versus depth of the multilayer body determined by time-of-flight secondary ion mass spectrometry, detection intensities of C6 ions have a maximum value at a depth of greater than 0 nm and 2.5 nm or less from an exposed surface. Detection intensities of C3 ions have a maximum value at a depth of greater than 0 nm and 3.0 nm or less from the exposed surface. Detection intensities of SiC4 ions have a maximum value at a depth of 0.5 nm or greater and 5.0 nm or less from the exposed surface. Detection intensities of SiC ions have a maximum value at a depth of 0.5 nm or greater and 10.0 nm or less from the exposed surface. Detection intensities of Si2 ions have a maximum value at a depth of 0.5 nm or greater and 10.0 nm or less from the exposed surface.Type: ApplicationFiled: September 20, 2019Publication date: March 3, 2022Inventors: Fuminori MITSUHASHI, Yasunori TATENO, Masahiro ADACHI, Yoshiyuki YAMAMOTO
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Publication number: 20220059683Abstract: A semiconductor device includes a graphene film disposed on a substrate and formed of atomic layers of graphene that are stacked, a source electrode and a drain electrode disposed on the graphene film, and a gate electrode disposed on the graphene film between the source electrode and the drain electrode with a gate insulator film interposed between the gate electrode and the graphene film, wherein a first number of the atomic layers of the graphene film in a source region where the source electrode is located and a drain region where the drain electrode is located is greater than a second number of the atomic layers of the graphene film in a channel region where the gate electrode is located.Type: ApplicationFiled: August 10, 2021Publication date: February 24, 2022Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yasunori TATENO, Fuminori MITSUHASHI
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Patent number: 10580869Abstract: A stacked body includes: a substrate made of silicon carbide and having a first main surface forming an angle of 20° or less with a silicon plane; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of silicon carbide forming the substrate. In an exposed surface of the graphene film which is a main surface opposite to the substrate, an area ratio of a region having a full width at half maximum of G? of 40 cm?1 or less under Raman spectroscopy analysis is 50% or more. Accordingly, the stacked body is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.Type: GrantFiled: April 19, 2017Date of Patent: March 3, 2020Assignees: Sumitomo Electric Industries, Ltd., Tohoku UniversityInventors: Masaya Okada, Fuminori Mitsuhashi, Yasunori Tateno, Masaki Ueno, Maki Suemitsu, Hirokazu Fukidome
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Patent number: 10529807Abstract: A stacked body includes: a substrate made of silicon carbide and having a first main surface forming an angle of 20° or less with a carbon plane; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of silicon carbide forming the substrate. In an exposed surface of the graphene film as seen in plan view, 10 or less regions are present per 1 mm2, the exposed surface being a main surface opposite to the substrate, and the regions each including 10 or more graphene layers and having a circumcircle with a diameter of 5 ?m or more and 100 ?m or less. Accordingly, the stacked body is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.Type: GrantFiled: April 19, 2017Date of Patent: January 7, 2020Assignees: Sumitomo Electric Industries, Ltd., Tohoku UniversityInventors: Masaya Okada, Fuminori Mitsuhashi, Masaki Ueno, Yasunori Tateno, Maki Suemitsu, Hirokazu Fukidome
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Patent number: 10283594Abstract: A silicon carbide (SiC) structure and a method of forming the SiC structure are disclosed. The SiC structure includes an SiC substrate and a film provided on the SiC substrate. The SiC substrate contains both of a hexagonal close packed (hcp) structure and a face centered cubic (fcc) structure, and has only one of the hcp surface and the fcc surface, where the hcp surface includes atoms in the topmost layer whose rows overlap with rows of atoms in the third layer, while, the fcc surface includes atoms in the topmost layer whose rows are different from rows of atoms in the third layer.Type: GrantFiled: September 1, 2017Date of Patent: May 7, 2019Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., TOHOKU UNIVERSITYInventors: Hiroyuki Nagasawa, Maki Suemitsu, Hirokazu Fukidome, Yasunori Tateno, Fuminori Mitsuhashi, Masaya Okada, Masaki Ueno
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Patent number: 10217823Abstract: An electron device having a channel layer made of graphene is disclosed. The electron device includes a graphene layer on a substrate, and a source electrode, a drain electrode, and a gate insulating film on the graphene layer. The electron device further includes a first gate electrode on the gate insulating film between the source electrode and the drain electrode, and a second gate electrode within the substrate. For the second gate electrode, another gate insulating film is on the graphene layer, or alternatively, a part of the substrate is interposed between the second gate electrode and the channel layer.Type: GrantFiled: December 13, 2017Date of Patent: February 26, 2019Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., TOHOKU UNIVERSITYInventors: Yasunori Tateno, Masaki Ueno, Masaya Okada, Fuminori Mitsuhashi, Maki Suemitsu, Hirokazu Fukidome
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Patent number: 10083831Abstract: A substrate includes: a support substrate having a first main surface and a surface layer region which includes at least the first main surface and is formed of any one material selected from the group consisting of boron nitride, molybdenum disulfide, tungsten disulfide, niobium disulfide, and aluminum nitride; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of the material forming the surface layer region. Accordingly, the substrate is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.Type: GrantFiled: March 9, 2017Date of Patent: September 25, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventors: Masaya Okada, Fuminori Mitsuhashi, Yasunori Tateno, Masaki Ueno
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Publication number: 20180166537Abstract: An electron device having a channel layer made of graphene is disclosed. The electron device includes a graphene layer on a substrate, electrodes of source, drain, and a gate insulating film on the graphene layer. The electron device further includes a firs gate electrode on the gate insulating film between the source electrode and the drain electrode, and further includes a second gate electrode within the substrate. The second gate electrode puts another gate insulating film against the graphene layer, or a part of the substrate.Type: ApplicationFiled: December 13, 2017Publication date: June 14, 2018Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., TOHOKU UNIVERSITYInventors: Yasunori Tateno, Masaki Ueno, Masaya Okada, Fuminori Mitsuhashi, Maki Suemitsu, Hirokazu Fukidome
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Publication number: 20180130912Abstract: A field effect transistor (FET) including a graphene layer as a carrier transporting channel is disclosed. The FET provides, on a substrate, a graphene layer, and electrodes of the source and drain on the graphene layer. The FET further provides a couple of gate electrodes and a supplemental electrode, where the former two gate electrodes are provided on a gate insulating film, while, the latter one is provided on the graphene layer and between two gate electrodes. The second gate electrode provided closer to the drain electrode has a gate length that is shorter than the gate length of the first gate electrode provided closer to the source electrode.Type: ApplicationFiled: November 6, 2017Publication date: May 10, 2018Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., TOHOKU UNIVERSITYInventors: Yasunori TATENO, Masaki UENO, Masaya OKADA, Fuminori MITSUHASHI, Maki SUEMITSU, Hirokazu FUKlDOME
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Publication number: 20180069081Abstract: A silicon carbide (SiC) structure and a method of forming the SiC structure are disclosed. The SiC structure includes an SiC substrate and a film provided on the SiC substrate. The SiC substrate contains both of a hexagonal close packed (hcp) structure and a face centered cubic (fcc) structure, and has only one of the hcp surface and the fcc surface, where the hcp surface includes atoms in the topmost layer whose rows overlap with rows of atoms in the third layer, while, the fcc surface includes atoms in the topmost layer whose rows are different from rows of atoms in the third layer.Type: ApplicationFiled: September 1, 2017Publication date: March 8, 2018Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., TOHOKU UNIVERSITYInventors: Hiroyuki NAGASAWA, Maki SUEMITSU, Hirokazu FUKlDOME, Yasunori TATENO, Fuminori MITSUHASHI, Masaya OKADA, Masaki UENO
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Patent number: 9825134Abstract: A layered semiconductor includes a base layer including a substrate and a buffer layer, and a drift layer which is disposed on the base layer and is made of GaN and whose conductivity type is an n-type. The drift layer has an average n-type impurity concentration of 1.5×1016 cm?3 or less in a radial direction of the substrate, and the difference between the maximum n-type impurity concentration and the minimum n-type impurity concentration is 1.5×1015 cm?3 or less.Type: GrantFiled: June 2, 2015Date of Patent: November 21, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Fuminori Mitsuhashi, Yusuke Yoshizumi, Takashi Ishizuka, Masaki Ueno
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Patent number: 9806156Abstract: A laminated body includes: a substrate portion composed of silicon carbide; and a graphene film disposed on a first main surface of the substrate portion, the graphene film having an atomic arrangement oriented with respect to an atomic arrangement of the silicon carbide of the substrate portion. A region in which a value of G?/G in Raman spectrometry is not less than 1.2 is not less than 10% in an area ratio in an exposed surface of the graphene film, the exposed surface being a main surface of the graphene film opposite to the substrate portion.Type: GrantFiled: November 4, 2016Date of Patent: October 31, 2017Assignees: Sumitomo Electric Industries, Ltd., Tohoku UniversityInventors: Fuminori Mitsuhashi, Takashi Ishizuka, Masaki Ueno, Yoshihiro Tsukuda, Yasunori Tateno, Maki Suemitsu, Hirokazu Fukidome, Hiroyuki Nagasawa
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Publication number: 20170301759Abstract: A stacked body includes: a substrate made of silicon carbide and having a first main surface forming an angle of 20° or less with a carbon plane; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of silicon carbide forming the substrate. In an exposed surface of the graphene film as seen in plan view, 10 or less regions are present per 1 mm2, the exposed surface being a main surface opposite to the substrate, and the regions each including 10 or more graphene layers and having a circumcircle with a diameter of 5 ?m or more and 100 ?m or less. Accordingly, the stacked body is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.Type: ApplicationFiled: April 19, 2017Publication date: October 19, 2017Inventors: Masaya Okada, Fuminori Mitsuhashi, Masaki Ueno, Yasunori Tateno, Maki Suemitsu, Hirokazu Fukidome
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Publication number: 20170301758Abstract: A stacked body includes: a substrate made of silicon carbide and having a first main surface forming an angle of 20° or less with a silicon plane; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of silicon carbide forming the substrate. In an exposed surface of the graphene film which is a main surface opposite to the substrate, an area ratio of a region having a full width at half maximum of G? of 40 cm?1 or less under Raman spectroscopy analysis is 50% or more. Accordingly, the stacked body is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.Type: ApplicationFiled: April 19, 2017Publication date: October 19, 2017Inventors: Masaya Okada, Fuminori Mitsuhashi, Yasunori Tateno, Masaki Ueno, Maki Suemitsu, Hirokazu Fukidome
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Publication number: 20170263453Abstract: A substrate includes: a support substrate having a first main surface and a surface layer region which includes at least the first main surface and is formed of any one material selected from the group consisting of boron nitride, molybdenum disulfide, tungsten disulfide, niobium disulfide, and aluminum nitride; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of the material forming the surface layer region. Accordingly, the substrate is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.Type: ApplicationFiled: March 9, 2017Publication date: September 14, 2017Inventors: Masaya Okada, Fuminori Mitsuhashi, Yasunori Tateno, Masaki Ueno