Patents by Inventor Fuminori Sasaoka
Fuminori Sasaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7939886Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.Type: GrantFiled: November 22, 2005Date of Patent: May 10, 2011Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Oshima, Masato Itoi
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Publication number: 20090250750Abstract: A trench gate power MOSFET (1) of the present invention includes an n-type epitaxial layer (12), gates (18) and MOSFET cells. The gate (18) is disposed in a trench (14) formed in a surface of the n-type epitaxial layer (12). The MOSFET cell is formed on the surface of the n-type epitaxial layer (12) so as to be in contact with side surfaces of the trench (14). The trench gate power MOSFET (1) further includes a p-type isolation region (26) formed on the surface of the n-type epitaxial layer (12) and disposed between the MOSFET cells adjacent to each other in the extending direction of the trench (14) out of the MOSFET cells, and has a pn-junction diode formed between the p-type isolation region (26) and the n-type epitaxial layer (12). According to the trench gate power MOSFET (1) of the present invention, the increase of a diode leakage current with the elevation of temperature can be suppressed.Type: ApplicationFiled: September 21, 2005Publication date: October 8, 2009Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Oshima, Masato Itoi
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Patent number: 7573096Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.Type: GrantFiled: February 16, 2005Date of Patent: August 11, 2009Assignee: Shindengen Electric Manufacturing Co, Ltd.Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Ohshima, Masato Itoi
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Publication number: 20080315301Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.Type: ApplicationFiled: November 22, 2005Publication date: December 25, 2008Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Oshima, Masato Itoi
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Publication number: 20080135925Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.Type: ApplicationFiled: February 16, 2005Publication date: June 12, 2008Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Ohshima, Masato Itoi
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Patent number: 7193268Abstract: In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction orthogonal to the N+ type source areas and the gate trenches. Thus, the N+ type source areas and a P type body layer are formed in a laminated state, but the P+ type diffusion areas are not laminated. Therefore, the structure of a mesa section is extremely simple. Furthermore, gate electrode films are connected to one another by a connection member. Thus, the semiconductor device has such a structure as to easily secure electric connection to each gate electrode film from outside. According to the foregoing structure, it is possible to extremely ease the miniaturization of the semiconductor device.Type: GrantFiled: January 13, 2005Date of Patent: March 20, 2007Assignee: Shindengen Electric Manufacturing Co., LtdInventors: Toshiyuki Takemori, Fuminori Sasaoka, Yuji Watanabe
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Publication number: 20060151828Abstract: In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction orthogonal to the N+ type source areas and the gate trenches. Thus, the N+ type source areas and a P type body layer are formed in a laminated state, but the P+ type diffusion areas are not laminated. Therefore, the structure of a mesa section is extremely simple. Furthermore, gate electrode films are connected to one another by a connection member. Thus, the semiconductor device has such a structure as to easily secure electric connection to each gate electrode film from outside. According to the foregoing structure, it is possible to extremely ease the miniaturization of the semiconductor device.Type: ApplicationFiled: January 13, 2005Publication date: July 13, 2006Inventors: Toshiyuki Takemori, Fuminori Sasaoka, Yuji Watanabe