Abstract: The present invention relates to a high-speed data transmission system for efficiently transmitting large amounts of data within short periods of time. A DRAM comprises at least a memory cell, sense amplifiers, a /RAS signal input, a word line (WL) boost signal generator, a sense amplifier control signal-generator, and a sense amplifier drive signal-generator, wherein the memory cell is constituted by a plurality of banks, the sense amplifiers are provided in a corresponding plurality of numbers, the sense amplifier control signal-generator are provided in a plurality of numbers to correspond to the plurality of banks, and provision is made of external sense amplifier activating signal terminals which are connected to the sense amplifier control signal-generator in order to activate the sense amplifiers independently of the /RAS signal.

Abstract: The present invention relates to a high-speed data transmission system for efficiently transmitting large amounts of data within short periods of time. A DRAM comprises at least a memory cell, sense amplifiers, a /RAS signal input, a word line (WL) boost signal generator, a sense amplifier control signal-generator, and a sense amplifier drive signal-generator, wherein the memory cell is constituted by a plurality of banks, the sense amplifiers are provided in a corresponding plurality of numbers, the sense amplifier control signal-generator are provided in a plurality of numbers to correspond to the plurality of banks, and provision is made of external sense amplifier activating signal terminals which are connected to the sense amplifier control signal-generator in order to activate the sense amplifiers independently of the /RAS signal.

Abstract: The present invention relates to a high-speed data transmission system for efficiently transmitting large amounts of data within short periods of time. A DRAM comprises at least a memory cell, sense amplifiers, a /RAS signal input, a word line (WL) boost signal generator, a sense amplifier control signal-generator, and a sense amplifier drive signal-generator, wherein the memory cell is constituted by a plurality of banks, the sense amplifiers are provided in a corresponding plurality of numbers, the sense amplifier control signal-generator are provided in a plurality of numbers to correspond to the plurality of banks, and provision is made of external sense amplifier activating signal terminals which are connected to the sense amplifier control signal-generator in order to activate the sense amplifiers independently of the /RAS signal.

Abstract: A semiconductor storage device having a word-line voltage booster circuit includes: a plurality of word-lines connected to each memory cell array; a drive signal generation circuit for producing a word-line drive signal having a voltage higher than a power supply voltage; a decoder circuit for transmitting the word-line drive signal produced by the drive signal generation circuit, when the drive signal generation circuit is selected by an address signal; and a charging circuit connected to a signal path which transmits the word-line drive signal from the drive signal generation circuit to the decoder circuit. The charging circuit charges the signal path before the word-line drive signal is output to the signal path.