Abstract: The present invention provides an address resolution method for use in a multiprocessor system with distributed shared memory. The method allows users to change a memory configuration and a system configuration to increase system operation flexibility and to isolate errors. A cell controller indexes into an address resolution table using the high-order part of a processor-specified address. A write protection flag specifies whether to permit write access from other cells. An attempt to write-access a cell inhibited for write access causes a logical circuit to output an access exception signal.

Abstract: A high multiplexing degree or interleaving factor is achieved in a memory having banks of different capacities. A group judging circuit generates the relevant interleave group and addresses in such group on the basis of the start address and sub-bank number of each interleave. A bank selection circuit generates a sub-bank number and addresses in the sub-bank on the basis of the address in the group. A multiplier and adder generate addresses in the bank on the basis of the addresses in the sub-bank.

Abstract: A data processing system includes a memory access control unit having a cache memory, an address array, a plural storage stage recirculating address pipeline and a plural storage stage recirculating data pipeline. An address inquiry to the address array indicates whether or not corresponding data is stored in the cache memory. If the data is available from the cache memory, it is read out to a storage stage in the data pipeline and supplied to the requester. If the data is not available from the cache memory, an access request is sent to the main memory. Until there is a response from the main memory the requested address is recirculated in the address pipeline. The main memory supplies the requested data to a storage stage in the data pipeline, from which it is transferred to a requester. When data is to be written into a memory and the cache memory is not accessible, the data is recirculated in the data pipeline until access to the main memory is possible.