Patents by Inventor Fumio Horiguchi
Fumio Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7075820Abstract: A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.Type: GrantFiled: May 14, 2004Date of Patent: July 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamada, Fumio Horiguchi, Takashi Ohsawa, Yoshihisa Iwata, Yoshiaki Asao
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Patent number: 7042040Abstract: A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.Type: GrantFiled: January 23, 2004Date of Patent: May 9, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Fumio Horiguchi
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Patent number: 7042753Abstract: A memory cell is constituted by a TMR element and a MOS transistor. The source diffusion layer of the MOS transistor is connected to a source line and the drain diffusion layer of the transistor is connected to a TMR element via a local interconnection wire. The TMR element is held between the local interconnection wire and a bit line. The TMR element is constituted by stacked TMR layers. Each TMR layer is able to have two states, that is, a state in which spin directions are parallel and anti-parallel. Therefore, the TMR element stores four-value data. A current-driving line is set immediately below the TMR element.Type: GrantFiled: February 13, 2002Date of Patent: May 9, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Fumio Horiguchi
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Publication number: 20050141262Abstract: A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.Type: ApplicationFiled: May 14, 2004Publication date: June 30, 2005Inventors: Takashi Yamada, Fumio Horiguchi, Takashi Ohsawa, Yoshihisa Iwata, Yoshiaki Asao
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Patent number: 6891225Abstract: A semiconductor memory device comprising: a source diffusion layer formed on a semiconductor substrate and connected to a fixed potential line; a plurality of columnar semiconductor layers arranged in a matrix form and formed on the source diffusion layer and each having one end connected to the source diffusion layer commonly, the columnar semiconductor layer taking a first data state with a first threshold voltage that excessive majority carriers are accumulated in the columnar semiconductor layer, and a second data state with a second threshold voltage that excessive majority carriers are discharged from the columnar semiconductor layer; a plurality of drain diffusion layers each formed at the other end of the columnar semiconductor layer; a plurality of gate electrodes each opposed to the columnar semiconductor layer via a gate insulating film, and connected to the word line; a plurality of word lines each connected to corresponding the gate electrodes; and a plurality of bit lines each connected to correType: GrantFiled: September 7, 2001Date of Patent: May 10, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Fumio Horiguchi, Takashi Ohsawa
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Publication number: 20040150028Abstract: A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.Type: ApplicationFiled: January 23, 2004Publication date: August 5, 2004Inventor: Fumio Horiguchi
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Patent number: 6548848Abstract: Each of MIS transistors of a semiconductor memory device has a semiconductor layer (12); a source region (15) formed in the semiconductor layer; a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a first gate (13) which forms a channel in the channel body; a second gate (20) formed so as to control a potential of the channel body by a capacitive coupling; and a high concentration region (21) formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body.Type: GrantFiled: December 3, 2001Date of Patent: April 15, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Fumio Horiguchi, Takashi Ohsawa, Yoshihisa Iwata, Takashi Yamada
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Publication number: 20020149962Abstract: A memory cell is constituted by a TMR element and a MOS transistor. The source diffusion layer of the MOS transistor is connected to a source line and the drain diffusion layer of the transistor is connected to a TMR element via a local interconnection wire. The TMR element is held between the local interconnection wire and a bit line. The TMR element is constituted by stacked TMR layers. Each TMR layer is able to have two states, that is, a state in which spin directions are parallel and anti-parallel. Therefore, the TMR element stores four-value data. A current-driving line is set immediately below the TMR element.Type: ApplicationFiled: February 13, 2002Publication date: October 17, 2002Inventor: Fumio Horiguchi
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Publication number: 20020130341Abstract: Each of MIS transistors of a semiconductor memory device has a semiconductor layer (12); a source region (15) formed in the semiconductor layer; a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a first gate (13) which forms a channel in the channel body; a second gate (20) formed so as to control a potential of the channel body by a capacitive coupling; and a high concentration region (21) formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body.Type: ApplicationFiled: December 3, 2001Publication date: September 19, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Fumio Horiguchi, Takashi Ohsawa, Yoshihisa Iwata, Takashi Yamada
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Publication number: 20020034855Abstract: A semiconductor memory device comprising: a source diffusion layer formed on a semiconductor substrate and connected to a fixed potential line; a plurality of columnar semiconductor layers arranged in a matrix form and formed on the source diffusion layer and each having one end connected to the source diffusion layer commonly, the columnar semiconductor layer taking a first data state with a first threshold voltage that excessive majority carriers are accumulated in the columnar semiconductor layer, and a second data state with a second threshold voltage that excessive majority carriers are discharged from the columnar semiconductor layer; a plurality of drain diffusion layers each formed at the other end of the columnar semiconductor layer; a plurality of gate electrodes each opposed to the columnar semiconductor layer via a gate insulating film, and connected to the word line; a plurality of word lines each connected to corresponding the gate electrodes; and a plurality of bit lines each connected to correType: ApplicationFiled: September 7, 2001Publication date: March 21, 2002Inventors: Fumio Horiguchi, Takashi Ohsawa
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Publication number: 20020030214Abstract: A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.Type: ApplicationFiled: September 12, 2001Publication date: March 14, 2002Inventor: Fumio Horiguchi
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Patent number: 6292390Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.Type: GrantFiled: January 8, 2001Date of Patent: September 18, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Koji Sakui, Takehiro Hasegawa, Shigeyoshi Watanabe, Fujio Masuoka, Tsuneaki Fuse, Toshiki Seshita, Seiichi Aritome, Akihiro Nitayama, Fumio Horiguchi
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Patent number: 6232822Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.Type: GrantFiled: June 30, 1994Date of Patent: May 15, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Koji Sakui, Takehiro Hasegawa, Shigeyoshi Watanabe, Fujio Masuoka, Tsuneaki Fuse, Toshiki Seshita, Seiichi Aritome, Akihiro Nitayama, Fumio Horiguchi
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Patent number: 5895946Abstract: A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.Type: GrantFiled: January 14, 1998Date of Patent: April 20, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Hamamoto, Fumio Horiguchi
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Patent number: 5731609Abstract: A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.Type: GrantFiled: February 24, 1997Date of Patent: March 24, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Hamamoto, Fumio Horiguchi
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Patent number: 5561311Abstract: A semiconductor memory having memory cells is formed on a semiconductor substrate. Each of the memory cells has a transistor and a capacitor. The transistor includes a channel region, a drain region and a source region aligned in a line and being insulated by an insulation film from an adjacent cell. Each of the memory cells has a gate electrode formed on the channel region with a gate insulating film therebetween. A pad electrode makes electrical contact with one of the source and drain regions of the memory cell and extends over the insulation film. A bit line makes electrical contact with the pad electrode above, extends in parallel to the line and is laterally isolated from one of the source and drain regions. A first insulating film is formed on the semiconductor substrate over the bit line.Type: GrantFiled: November 29, 1994Date of Patent: October 1, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Hamamoto, Fumio Horiguchi, Katsuhiko Hieda
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Patent number: 5488242Abstract: In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.Type: GrantFiled: November 24, 1993Date of Patent: January 30, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Sunouchi, Hiroshi Takato, Tohru Ozaki, Naoko Okabe, Katsuhiko Hieda, Fumio Horiguchi, Akihiro Nitayama, Takashi Yamada, Kouji Hasimoto, Satosi Inoue
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Patent number: 5477071Abstract: A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.Type: GrantFiled: April 7, 1995Date of Patent: December 19, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Hamamoto, Fumio Horiguchi
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Patent number: 5387532Abstract: A semiconductor memory has many memory cells of which each has a transistor and a capacitor. In each memory cell, one of source and drain regions of the transistor is connected to a bit line formed above the transistor. The capacitor includes a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line.To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor. A bit line is formed and connected to one of the source and drain regions.Type: GrantFiled: August 10, 1993Date of Patent: February 7, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Hamamoto, Fumio Horiguchi, Katsuhiko Hieda
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Patent number: 5371024Abstract: A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented.Type: GrantFiled: September 21, 1992Date of Patent: December 6, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Fumio Horiguchi, Hiroshi Takato, Fujio Masuoka