Abstract: A wiring board includes a core substrate having a number of through-holes, and buildup insulating layers and buildup wiring layers alternately laminated on upper and lower surfaces of the core substrate, in which a first through-hole group is arranged in a first region in the core board at a first arrangement density, the first region being opposed to the semiconductor element connection pad formation region, a second through-hole group is arranged in a second region at a second arrangement density lower than the first arrangement density, the second region being located in an outer peripheral portion of the core substrate and away from the first region, and a third through-hole group is arranged in a third region at a third arrangement density higher than the second arrangement density, the third region being located between the first region and the second region.

Abstract: A wiring board includes a core substrate having a number of through-holes, and buildup insulating layers and buildup wiring layers alternately laminated on upper and lower surfaces of the core substrate, in which a first through-hole group is arranged in a first region in the core board at a first arrangement density, the first region being opposed to the semiconductor element connection pad formation region, a second through-hole group is arranged in a second region at a second arrangement density lower than the first arrangement density, the second region being located in an outer peripheral portion of the core substrate and away from the first region, and a third through-hole group is arranged in a third region at a third arrangement density higher than the second arrangement density, the third region being located between the first region and the second region.

Abstract: A method of manufacturing a printed circuit board is disclosed. A seed layer is removed while etching of a circuit pattern is prevented. In a printed circuit board manufacturing process according to a semi-additive method, a seed layer is formed by electroless copper plating. Using a resist pattern, a circuit pattern is formed by electrolytic copper plating. After the formation of the circuit pattern, the exposed regions of seed layer are subjected to etching. According to the invention, an etching liquid at a temperature of about 15° C. or less is used. As a temperature of the etching liquid is lowered, a potential difference between the seed layer and the circuit pattern increases. Due to the increase in potential difference, the seed layer becomes more susceptible to being etched, while the circuit pattern becomes less susceptible to being etched.