Abstract: A semiconductor memory device including an address decode signal transmission circuit comprising address buffers; a predecoder; address buses provided before a main decode; a transmission circuit for outputting predecoded signals to the address buses while limiting amplitude thereof; and a receiving circuit provided before the main decoder for differentially amplifying signals from the address buses, wherein the memory cell array is divided into a plural number of sub-blocks and power can be selectively supplied to at least one of the sub-blocks.

Abstract: A static RAM in which the threshold voltage of the drive transistors of a memory cell is higher than the threshold voltage of the access transistors, and in which the impedance of the access transistors is lower during writing then during reading, for improving data retention properties of the memory cell. The bit or data lines for reading data from the memory cell is provided with an equalizing circuit and data writing is performed from a writing buffer circuit. This writing buffer circuit is controlled by a pulse generator generating a pulse of a constant predetermined width on the basis of detected address transition to maintain a constant cycle time duration even on the occasion of a continuous write operation.

Abstract: The invention provides an improved semiconductor memory device such as a static RAM. The semiconductor memory device attains high speed read-out of data therefrom without increasing a step of production process. The semiconductor memory device further attains a flash-clearing function without increasing the size of a chip thereof.

Abstract: The invention provides an improved semiconductor memory device such as a static RAM. The semiconductor memory device attains high speed read-out of data therefrom without increasing a step of production process. The semiconductor memory device further attains a flash-clearing function without increasing the size of a chip thereof.

Abstract: In a static RAM having an internal low voltage transformation circuit, a word line drive circuit is provided which applies a low voltage, from an internal low voltage transformation circuit to a word line during read-out to improve the static RAM operating margin. The internal low voltage transformation circuit is formed by a reference voltage supply circuit and an internal voltage control circuit. A data hold voltage is supplied, when the static RAM is operating at a lower voltage, by a power pull-down device having a lower power consumption than the internal low voltage transformation circuit so as to achieve power consumption savings.