Patents by Inventor Fumio Murakami
Fumio Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134310Abstract: An object of the present invention is to provide a developer supply container capable of simplifying a mechanism for displacing a developer receiving portion to connect it with a developer supply container. A developer supply container 1 for supplying a developer through a developer receiving portion 11 displaceably provided in a developer receiving apparatus 8 to which said developer supply container 1 is detachably mountable, said developer supply container 1 includes a developer accommodating portion 2c for accommodating a developer; and an engaging portions 3b2, 3b4, engageable with said developer receiving portion 11, for displacing said developer receiving portion 11 toward said developer supply container 1 with a mounting operation of said developer supply container 1 to establish a connected state between said developer supply container 1 and said developer receiving portion 11.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Manabu Jimba, Ayatomo Okino, Katsuya Murakami, Toshiaki Nagashima, Fumio Tazawa
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Patent number: 7803660Abstract: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.Type: GrantFiled: December 9, 2008Date of Patent: September 28, 2010Assignee: Renesas Electronics CorporationInventors: Fumio Murakami, Kenichi Imura, Makoto Araki
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Publication number: 20090093087Abstract: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.Type: ApplicationFiled: December 9, 2008Publication date: April 9, 2009Inventors: Fumio MURAKAMI, Kenichi Imura, Makoto Araki
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Patent number: 7465609Abstract: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.Type: GrantFiled: August 30, 2005Date of Patent: December 16, 2008Assignee: Renesas Technology Corp.Inventors: Fumio Murakami, Kenichi Imura, Makoto Araki
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Patent number: 7144755Abstract: At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.Type: GrantFiled: August 19, 2004Date of Patent: December 5, 2006Assignees: Renesas Technology Corp., Eastern Japan Semiconductor Technologies, Inc.Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami
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Publication number: 20060125064Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.Type: ApplicationFiled: February 1, 2006Publication date: June 15, 2006Inventors: Fujio Ito, Hiromichi Suzuki, Hiroyuki Takeno, Hiroshi Shimoji, Fumio Murakami, Keiko Kurakawa
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Patent number: 7019388Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.Type: GrantFiled: December 9, 2003Date of Patent: March 28, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Renesas Eastern Japan Semiconductor, Inc.Inventors: Fujio Ito, Hiromichi Suzuki, Hiroyuki Takeno, Hiroshi Shimoji, Fumio Murakami, Keiko Kurakawa
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Publication number: 20060046340Abstract: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.Type: ApplicationFiled: August 30, 2005Publication date: March 2, 2006Inventors: Fumio Murakami, Kenichi Imura, Makoto Araki
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Publication number: 20050019979Abstract: At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.Type: ApplicationFiled: August 19, 2004Publication date: January 27, 2005Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami
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Patent number: 6797542Abstract: At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.Type: GrantFiled: February 12, 2003Date of Patent: September 28, 2004Assignees: Renesas Technology Corp., Eastern Japan Semiconductor Technologies, Inc.Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami
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Publication number: 20040124506Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.Type: ApplicationFiled: December 9, 2003Publication date: July 1, 2004Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Renesas Eastern Japan Semiconductor, Inc.Inventors: Fujio Ito, Hiromichi Suzuki, Hiroyuki Takeno, Hiroshi Shimoji, Fumio Murakami, Keiko Kurakawa
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Publication number: 20030153130Abstract: At the time of performing a resin molding for a matrix frame in the fabrication of a semiconductor integrated circuit device, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of product obtained.Type: ApplicationFiled: February 12, 2003Publication date: August 14, 2003Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami
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Patent number: 5349728Abstract: A magnetic marker comprising a plurality of magnetized fibers oriented substantially parallel to each other is attached to a fringe of ground fabric for production of felt in the form of an endless belt for detecting the travel of the ground fabric and changing various production parameters according to the number of turns which the ground fabric makes around a series of rolls for causing the movement of the ground fabric. Since the magnetic marker consists of extremely thin magnetized fibers, it can withstand the repeated piercing by needles which is required for the production of felt for the purpose of entangling the fibers of fiber web with the ground fabric.Type: GrantFiled: May 27, 1992Date of Patent: September 27, 1994Assignee: Nippon Felt Co., Ltd.Inventors: Fumio Murakami, Eiichi Morita, Tokuji Iwasaki, Yasushi Suzuki, Kouha Fujimoto
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Patent number: 5016677Abstract: An automatic cop changing device for a weaving machine in which a shuttle carrying a cop consisting of a bobbin around which a weft is wound is reciprocated between warps so as to weave the weft between the warps, comprising: a cop positioning unit for securing the shuttle stationary near a terminal point of its reciprocating movement when the weft of a current cop mounted on the shuttle is consumed by more than a precribed amount; a cop storage unit for storing a plurlaity of new cops; a robot arm carrying a weft gripping hand for drawing the weft from the current cop and a weft from one of the new cops stored in the cop storage unit, and crossing the two wefts, a cop engaging hand for moving the cop in the shuttle between its upright position and its retracted position, and a cop gripping hand for removing the old cop from the shuttle and carrying the new cop into the shuttle; a weft tying unit for tying the crossed part of the wefts; and a weft trimming unit for trimming an extraneous part of the tied weftType: GrantFiled: November 29, 1989Date of Patent: May 21, 1991Assignee: Nippon Felt Co., Ltd.Inventors: Fumio Murakami, Sadaaki Okazaki, Takayoshi Aoyagi, Tokuji Iwasaki, Tetsuya Konno
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Patent number: 4200796Abstract: A storage cell type X-ray apparatus uses a storage cell as its power source and operates so that the dc voltage of the power source is converted to an ac voltage, this ac voltage is elevated to a higher voltage and rectified to obtain a high dc voltage. The resulting voltage is applied to an X-ray tube, to cause this X-ray tube to emit X-rays. This apparatus includes means for stabilizing the voltage applied to the X-ray tube.Type: GrantFiled: June 15, 1978Date of Patent: April 29, 1980Assignee: Hitachi Medical CorporationInventors: Fumio Murakami, Takeshi Enya, Yoshinori Ochiai