Abstract: An output buffer circuit which supplies at an emitter coupled logic (ECL) level logic signals from a logic circuit in an integrated circuit realized by a CMOS process. The logic signals are supplied to the gate electrodes of a first P-channel CMOS transistor and a first N-channel CMOS transistor connected in series. A second P-channel CMOS transistor for amplifying the output signal has an open drain configuration. Between the output terminal of the output from the P-channel CMOS transistor of open drain configuration and an external power supply terminal is connected a first resistor. Voltage regulating means, connected between the output terminal and the external power supply terminal, regulates the output voltage at the output terminal. In the voltage regulating means, a voltage setting circuit produces a desired voltage from a voltage supplied from the external power supply terminal.

Abstract: A digital-to-analog (D/A) converter for converting a n-bit digital 2's complement signal to an analog signal. The D/A converter consists of a controller, a capacitor array, and a switch array. The controller operates to convert a 2's complement digital input signal into a 1's complement digital signal. The capacitor array consists of (n-1) capacitors each being connected at one electrode to a common output terminal. The switch array consists of (n-1) switches each connected individually to the remaining electrodes of the (n-1) capacitors. The switch array applies either one of a first or a second reference voltage to the (n-1) capacitors in response a second controller signal. An additional capacitor and switch are connected to the capacitor and switch arrays which serve to convert a digital signal from 2's complement to 1's complement.