Patents by Inventor Fumio Tahara
Fumio Tahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170253995Abstract: A method for heat-treating a silicon single crystal wafer by an RTA treatment, including: putting a silicon single crystal wafer having an Nv region for the entire plane of the silicon single crystal wafer or an Nv region containing an OSF region for the silicon single crystal wafer entire plane into an RTA furnace, performing pre-heating at temperature lower than temperature at which silicon reacts with NH3 while supplying gas that contains NH3 into the RTA furnace, subsequently stopping the supply of the gas containing NH3 and starting supply of Ar gas to start an RTA treatment under Ar gas atmosphere in which the NH3 gas remains. This provide a method for heat-treating a silicon single crystal wafer that give gettering capability without degrading TDDB properties even to a silicon single crystal wafer in which the entire plane is an Nv region or an Nv region containing an OSF region.Type: ApplicationFiled: September 17, 2015Publication date: September 7, 2017Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng QU, Fumio TAHARA, Masahiro SAKURADA, Shuji TAKAHASHI
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Patent number: 9708726Abstract: A silicon wafer heat treatment method includes: placing a silicon wafer on a SiC jig and into a heat treatment furnace; performing heat treatment on the silicon wafer in the heat treatment furnace in a first non-oxidizing atmosphere; reducing the temperature; and carrying the silicon wafer out of the heat treatment furnace. In the heat reduction step, after the temperature is reduced to the temperature at which the silicon wafer can be carried out of the heat treatment furnace, the first non-oxidizing atmosphere is switched to an atmosphere containing oxygen, an oxide film having a thickness of 1 to 10 nm is formed on the surface of the SiC jig in the atmosphere containing oxygen, and the atmosphere containing oxygen is then switched to a second non-oxidizing atmosphere. A silicon wafer heat treatment method can prevent carbon contamination from a jig and an environment during a heat treatment process.Type: GrantFiled: June 26, 2014Date of Patent: July 18, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng Qu, Fumio Tahara
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Patent number: 9606030Abstract: A method for detecting a crystal defect in a silicon single crystal wafer doped with nitrogen, the silicon single crystal wafer whose initial oxygen concentration is 8 ppma (JEIDA) or lower. The method further includes the steps of: making a crystal defect of defect size of 25 nm or smaller apparent and detectable by implanting oxygen into the crystal defect by performing heat treatment on the silicon single crystal wafer in an oxygen atmosphere; and detecting the crystal defect of the silicon single crystal wafer after the heat treatment temperature is set such that, when the ratio between the oxygen solid solubility and the initial oxygen concentration of the silicon single crystal wafer heat treatment is set at ?=the oxygen solid solubility/the initial oxygen concentration, ? falls within a range from 1 to 3.Type: GrantFiled: June 18, 2012Date of Patent: March 28, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi
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Publication number: 20160130718Abstract: A silicon wafer heat treatment method includes: placing a silicon wafer on a SiC jig and into a heat treatment furnace; performing heat treatment on the silicon wafer in the heat treatment furnace in a first non-oxidizing atmosphere; reducing the temperature; and carrying the silicon wafer out of the heat treatment furnace. In the heat reduction step, after the temperature is reduced to the temperature at which the silicon wafer can be carried out of the heat treatment furnace, the first non-oxidizing atmosphere is switched to an atmosphere containing oxygen, an oxide film having a thickness of 1 to 10 nm is formed on the surface of the SiC jig in the atmosphere containing oxygen, and the atmosphere containing oxygen is then switched to a second non-oxidizing atmosphere. A silicon wafer heat treatment method can prevent carbon contamination from a jig and an environment during a heat treatment process.Type: ApplicationFiled: June 26, 2014Publication date: May 12, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng QU, Fumio TAHARA
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Publication number: 20150287630Abstract: A method of manufacturing an SOI wafer, includes, before forming an oxide film, heat treating a prepared silicon wafer at a temperature ranging from 1100° C. to 1250° C. under an oxidizing atmosphere for 30 minutes to 120 minutes and polishing a surface of the silicon wafer subjected to the heat treatment, which will become a bonding interface. The method can sufficiently dissolve defects in a bond wafer in SOI-wafer manufacture and manufacture an SOI wafer with few faults such as defects. The method also can repeatedly reuse a separated wafer, which is produced as a by-product in the ion implantation separation method, as the bond wafer.Type: ApplicationFiled: September 12, 2013Publication date: October 8, 2015Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi
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Patent number: 8916953Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.Type: GrantFiled: January 6, 2012Date of Patent: December 23, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Shu Sugisawa
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Patent number: 8900971Abstract: The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.Type: GrantFiled: January 6, 2012Date of Patent: December 2, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
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Patent number: 8877609Abstract: A method for manufacturing a bonded substrate that has an insulator layer in part of the bonded substrate includes: partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; performing a heat treatment to the base substrate having the porous layer formed thereon to change the porous layer into the insulator layer, and thereby forming the insulator layer whose thickness partially varies on the bonding surface of the base substrate; removing the insulator layer whose thickness varies by an amount corresponding to a thickness of a small-thickness portion by etching; bonding the bonding surface of the base substrate on which an unetched remaining insulator layer is exposed to a bond substrate; and reducing a thickness of the bonded bond substrate and thereby forming a thin film layer.Type: GrantFiled: April 10, 2012Date of Patent: November 4, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
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Publication number: 20140120695Abstract: A method for manufacturing a bonded substrate that has an insulator layer in part of the bonded substrate includes: partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; performing a heat treatment to the base substrate having the porous layer formed thereon to change the porous layer into the insulator layer, and thereby forming the insulator layer whose thickness partially varies on the bonding surface of the base substrate; removing the insulator layer whose thickness varies by an amount corresponding to a thickness of a small-thickness portion by etching; bonding the bonding surface of the base substrate on which an unetched remaining insulator layer is exposed to a bond substrate; and reducing a thickness of the bonded bond substrate and thereby forming a thin film layer.Type: ApplicationFiled: April 10, 2012Publication date: May 1, 2014Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yuuki Ooi, Wei Feng Qu, Tsuyoshi Ohtsuki, Kyoko Mitani, Fumio Tahara
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Publication number: 20140119399Abstract: A method for detecting a crystal defect in a silicon single crystal wafer doped with nitrogen, the silicon single crystal wafer whose initial oxygen concentration is 8 ppma (JEIDA) or lower. The method further includes the steps of: making a crystal defect of defect size of 25 nm or smaller apparent and detectable by implanting oxygen into the crystal defect by performing heat treatment on the silicon single crystal wafer in an oxygen atmosphere; and detecting the crystal defect of the silicon single crystal wafer after the heat treatment temperature is set such that, when the ratio between the oxygen solid solubility and the initial oxygen concentration of the silicon single crystal wafer heat treatment is set at ?=the oxygen solid solubility/the initial oxygen concentration, ? falls within a range from 1 to 3.Type: ApplicationFiled: June 18, 2012Publication date: May 1, 2014Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi
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Publication number: 20130341763Abstract: The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.Type: ApplicationFiled: January 6, 2012Publication date: December 26, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yuuki Ooi, Wei Feng Qu, Tsuyoshi Ohtsuki, Kyoko Mitani, Fumio Tahara
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Publication number: 20130264685Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.Type: ApplicationFiled: January 6, 2012Publication date: October 10, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Shu Sugisawa
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Patent number: 8551246Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.Type: GrantFiled: May 7, 2009Date of Patent: October 8, 2013Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
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Publication number: 20110045246Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.Type: ApplicationFiled: May 7, 2009Publication date: February 24, 2011Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
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Patent number: 7713851Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.Type: GrantFiled: August 3, 2005Date of Patent: May 11, 2010Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
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Publication number: 20080038526Abstract: A silicon epitaxial wafer 100 formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by a CZ method, and doped with boron so that a resistivity thereof is in the range of 0.009 ?·cm or higher and 0.012 ?·cm or lower. The silicon single crystal substrate 1 has a density of the oxygen precipitation nuclei of 1×1010 cm?3 or higher. A width of a no-oxygen-precipitation-nucleus-forming-region 15, formed between the silicon epitaxial layer 2 and the silicon single substrate 1, is in the range of more than 0 ?m and less than 10 ?m. Thereby, provided is a silicon epitaxial wafer using a boron doped p+ CZ substrate, wherein a formed width of no-oxygen-precipitation-nucleus-forming-region is reduced sufficiently, and oxygen precipitates can be formed having a density sufficient enough to exert an IG effect.Type: ApplicationFiled: July 5, 2005Publication date: February 14, 2008Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Fumitaka Kume, Tomosuke Yushida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
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Publication number: 20070269338Abstract: A silicon epitaxial wafer 100 is formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by means of a CZ method, and doped with boron so that a resistivity thereof is less than 0.018 ?·cm. The silicon single crystal substrate 1 has a density of bulk stacking faults 13 in the silicon single crystal substrate 1 in the range of 1×108 cm?3 or higher and 3×109 cm?3 or lower. Thereby, provided is a silicon epitaxial wafer having a boron doped p+ CZ substrate with a resistivity of 0.018?·cm or lower, and a state of formation of oxygen precipitates can be adjusted adequately so as to secure a sufficient IG effect and to suppress a problem of bow and deformation of a substrate, despite that sizes of oxygen precipitates is so small to be observed accurately.Type: ApplicationFiled: June 27, 2005Publication date: November 22, 2007Applicant: Shin-Etsu Handotai Co., LtdInventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
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Publication number: 20070243699Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.Type: ApplicationFiled: August 3, 2005Publication date: October 18, 2007Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara