Patents by Inventor Fumio Yoshioka

Fumio Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204003
    Abstract: A failure region is specified when a failure occurs in a non-volatile semiconductor memory. When a device controller reads data stored in a specific page in a plurality of non-volatile semiconductor memories to detect an uncorrectable error (UE) of the data stored in the specific page, the device controller executes a diagnosis process including specifying a specific storage circuit that is a storage circuit including the specific page, reading data stored in a part of blocks of the specific storage circuit, and specifying, on the basis of a result of reading data stored in the block, a failure region in the specific storage circuit.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: February 12, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kenta Ninose, Takuji Itou, Fumio Yoshioka, Takashi Tsunehiro, Go Uehara, Shigeo Homma
  • Publication number: 20160259675
    Abstract: A failure region is specified when a failure occurs in a non-volatile semiconductor memory. When a device controller reads data stored in a specific page in a plurality of non-volatile semiconductor memories to detect an uncorrectable error (UE) of the data stored in the specific page, the device controller executes a diagnosis process including specifying a specific storage circuit that is a storage circuit including the specific page, reading data stored in a part of blocks of the specific storage circuit, and specifying, on the basis of a result of reading data stored in the block, a failure region in the specific storage circuit.
    Type: Application
    Filed: August 27, 2014
    Publication date: September 8, 2016
    Applicant: HITACHI, LTD.
    Inventors: Kenta NINOSE, Takuji ITOU, Fumio YOSHIOKA, Takashi TSUNEHIRO, Go UEHARA, Shigeo HOMMA
  • Patent number: 4260999
    Abstract: A semiconductor device and a method of manufacturing the same, wherein there are provided, on a semiconductor substrate of a first conductivity type, a first and a second epitaxial layer each having a second conductivity type opposite to the first conductivity type. A plurality of regions are defined in the entire area of the epitaxial layer by being isolated by means of an isolation layer of the first conductivity type which extends from the surface of the second epitaxial layer to the semiconductor substrate. Furthermore, a first buried layer of the second conductivity type is formed in each of the isolated regions in such a manner as to extend in the first epitaxial layer and semiconductor substrate so that a transistor can be formed on each first buried layer.
    Type: Grant
    Filed: April 6, 1979
    Date of Patent: April 7, 1981
    Assignee: Toko, Inc.
    Inventor: Fumio Yoshioka